ATS'12
The 21st Asian Test Symposium November 19-22, 2012,Toki Messe Niigata Convetion Center, Niigata, Japan
Information Sponsor Scopes Submissions More Information Registration Registration Procedure Accomodation Procedure Online Registration ATS'12 Program ATS'12 at a Glance Advance Program Tutorial Visa Guide Visa Guide Conference Location The Venue Call for Papers PDF Paper Submission Regular Session Industry Session Committees Organizing Committee Program Committee Steering Committee Related Links WRTLT'12 PRDC'12 ATS'12 Advance Program Jump to November 19th, 20th, 21st, 22nd Nov. 19th, 2012 9:15-12:15 Tutorial 1 Beyond DFT: The Convergence of DFM, Variability, Yield, Diagnosis and Reliability S. Venkataraman (Intel), R. Aitken (ARM) 13:45-16:45 Tutorial 2 Power-Aware Testing and Test Strategies for Low Power Devices P. Girard (LIRMM), N. Nicolici (McMaster Univ.), X. Wen (Kyushu Inst. Tech.) Nov. 20th, 2012 9:30-10:40 Plenary Session 1 Keynote Address I: On-Chip Sensors to Support Parametric Test and Diagnosis J. A. Abraham (Univ. Texas) Keynote Address II: VLSI Design and Testing for Enhanced Systems Dependability S. Asai (CREST and Rigaku Corp.) 11:00-12:20 Plenary Session 2 Invited Talk I: 3-D Integration Technology and Future Trend M. Koyanagi (Tohoku Univ.) Invited Talk II: Next-Generation Testing: Towards a New Level of Abstraction P. Wohl (Synopsys) 13:40-15:40 Session 3A (Industry Session) 13:40-14:40 Oral Presentation 14:40-15:40 Poster Presentation An Effective At-speed Scan Testing Approach Using Multiple-Timing Clock Waveforms H. Iwata, Y. Maeda, J. Matsushima, M. Takakura (Renesas) LBIST/ATPG technologies used for on-demand digital logic testing in Automotive Circuits D. Meehl, B. Petrakis, P. Zhang (Cadence) Portable/Desktop Testing Solution for Engineering with Cloud N. Takahashi, T. Watanabe, T. Suzuki, M. Kimura (Advantest) Characteristics Variability Evaluation of Actual LSI Transistors with Nanoprobing M. Fukui, Y. Nara, J. Fuse (Hitach High-Tech.) F-matrix (ABCD-matrix) Circuit Simulation Built in IC Test Program H. Okawara (Advantest) Addressing Test Challenges in Advanced Technology Nodes Y. Zorian (Synopsys) 13:40-15:20 Session 3B Diagnosis and Debug Chair: H. -J Wunderlich (Univ. Stuttgart) Diagnosis of Cell Internal Defects With Multi-Cycle Test Patterns X. Fan (Univ. Iowa), M. Sharama, W. -T. Cheng (Mentor Graphics), S. M. Reddy (Univ. Iowa) Automated Post-Silicon Debugging of Failing Speedpaths M. Dehbashi (Univ. Bremen), G. Fey (German Aerospace Genter) SAT-based automatic rectification and debugging of combinational circuits with LUT insertions S. Jo, T. Matsumoto, M. Fujita (Univ. Tokyo) A new look ahead technique for customized testing in Digital Microfluidic Biochips P. Roy, H. Rahaman (Bengal Engineering and Science Univ.), P. Dasgupta (Indian Inst. Management) 13:40-15:20 Session 3C System-in-Package (SiP) / 3D IC Test Chair: D. Xiang (Tsinghua Univ.) TSV Stress-Aware ATPG for 3D Stacked ICs S. Deutsch, K. Chakrabarty (Duke Univ.), S. Panth, S. K. Lim (Georgia Inst. Tech.) Linear Programming Formulations for Thermal-Aware Test-Scheduling of 3D-Stacked Integrated Circuits S. K. Millican, K. K. Saluja (Univ. Wisconsin) Programmable Leakage Test and Binning for TSVs Y. -H. Lin, S. -Y. Huang (National Tsing Hua Univ.), K. -H. Tsai, W. -T. Cheng (Mentor Graphics) 15:40-17:20 Session 4A (Special Session 1) Quantum Informatics: Classical Circuit Synthesis, Resource Optimisation and Benchmarking Organizer: Ilia Polian (Univ. Passau) Counting Gates, Moving Qubits: Evaluating the Execution Cost of Quantum Circuits R. V. Meter (Keio Univ.) Programming a Topological Quantum Computer S. Devitt, K. Nemoto (National Inst. Info.) An Optimization Problem for Topological Quantum Computation S. Yamashita (Ritsumeikan Univ.) Classical challenge problems to realise a surface code quantum computer A. Fowler (Univ. Melbourne) 15:40-17:20 Session 4B (Special Session 2) Dependable VLSI Organizer: X. Gu (Huawei Tech.) Soft Error Issues with Scaling Technologies S. Baeg, J. Bae, S. Lee, C. S. Lim, S. H. Jeon, H. Lee (Hanyang Univ.) In-field Testing of NAND Flash Storage: Why and How? Y. Hu (ICT/CAS), X. Gu (Huawei Tech.), X. Li (ICT/CAS) A Few Design Techniques for "Dependability" of an SOC J. Qian (AMD) Accessing Embedded DfT Instruments with IEEE P1687 E. Larsson (Lund Univ.), F. G. Zadegan (Linkoping Univ.) 15:40-17:20 Session 4C Test Compaction / Test Quality Chair: T. Hosokawa (Nihon Univ.) Multi-Level EDT to Reduce Scan Channels in SoC Designs G. Li, J. Qian, P. Li, G. Zuo (AMD) On Utilizing Test Cube Properties to Reduce Test Data Volume Further X. Lin, J. Rajski (Mentor Graphics) Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage M. Arai, Y. Shimizu, K. Iwasaki (Tokyo Metropolitan Univ.) Tailoring Tests for Functional Binning of Integrated Circuits S. Sindia, V. D. Agrawal (Auburn Univ.) Nov. 21st, 2012 9:15-10:30 Session 5A Temperature / Power-Aware Test I Chair: M. Yoshimura (Kyushu Univ.) A Thermal-Driven Test Application Scheme for 3-Dimensional ICs D. Xiang, K. Shen, Y. Deng (Tsinghua Univ.) A Transition Isolation Scan Cell Design for Low Shift and Capture Power Y. -T. Lin, J. -L. Huang (National Taiwan Univ.), X. Wen (Kyushu Insti. Tech.) A Probabilistic and Constraint Based Approach for Low Power Test Generation H. Sabaghian-Bidgoli, M. Namaki-Shoushtari, Z. Navabi (Univ. Tehran) 9:15-10:30 Session 5B Dependable Systems / Memory Test Chair: S. Gupta (Univ. Southern California) Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection Y. Ohkawa, Y. Miura (Tokyo Metropolitan Univ.) Impact of Resistive-Bridge Defects in TAS-MRAM Architectures J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri (LIRMM), G. Prenat CEA/SPINTEC), J. Alvarez-Herault, K. Mackay (CROCUS Tech.) SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write Y. Fang, H. Li, X. Li (ICT/CAS) 9:15-10:30 Session 5C Design Verification and Validation / Software Design for Testing Chair: S. Fukumoto (Tokyo Metropolitan Univ.) A Generalized Theory for Formal Assertion Coverage S. Das (IIT Kharagpur), A. Banerjee (Indian Statistical Inst.), P. Dasgupta (IIT Kharagpur) Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods A. M. Gharehbaghi (JST), M. Fujita (Univ. Tokyo) Hardware-Accelerated Workload Characterization for Power Modeling and Fault Injection A. Krieg, J. Grinschgl, C. Steger, R. Weiss (Graz Univ.), H. Bock, J. Haid (Infineon Tech.), 10:50-12:30 Session 6A Temperature / Power-Aware Test II Chair: H. Li (ICT/CAS) Scan Test Power Simulation on GPGPUs S. Holst, E. Schneider, H. -J. Wunderlich (Univ. Stuttgart) Power Supply Noise Sensor based on Timing Uncertainty Measurements M. Valka, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel (LIRMM), P. Debaud, S. Guilhot (ST-Ericsson) Peak Power Estimation: a Case Study on CPU Cores P. Bernardi, M. D. Carvalho, E. Sanchez, M. S. Reorda (Politecnico di Torino), A. Bosio, L. Dilillo, P. Girard, M. Valka (LIRMM) Low Power BIST for Scan-Shift and Capture Power Y. Sato, S. Wang, T. Kato, K. Miyase, S. Kajihara (Kyushu Inst. Tech.) 10:50-12:30 Session 6B Analog Test and High-Speed I/O Test I Chair: M. Hashizume (Univ. Tokushima) Two-Tone Signal Generation for Communication Application ADC Testing K. Kato, F. Abe, K. Wakabayashi, C. Gao, T. Yamada, H. Kobayashi (Gunma Univ.), O. Kobayashi (STARC), K. Niitsu (Gunma Univ.) A New Procedure for Measuring High-Accuracy Probability Density Functions T. J. Yamaguchi (Advantest), K. Asada (Univ. Tokyo), K. Niitsu (Gunma Univ.), M. Abbas, S. Komatsu (Univ. Tokyo), H. Kobayashi (Gunma Univ.), J. A. Moreira (Advantest) Design of a High Bandwidth Interposer for Performance Evaluation of ATE Test Fixtures at the DUT Socket J. Moreira (Advantest) Spectral Estimation Based Acquisition of Incoherently Under-Sampled Periodic Signals : Application to Bandwidth Interleaving D. Bhatta, N. Tzou (Georgia Inst. Tech.), H. Choi (Samsung), A. Chatterjee (Georgia Inst. Tech.) 10:50-12:30 Session 6C Board and System Test Chair: K. -J. Lee (National Cheng Kung Univ.) Board-Level Functional Fault Diagnosis Using Learning Based on Incremental Support-Vector Machines F. Ye (Duke Univ.), Z. Zhang (Huawei Tech.), K. Chakrabarty (Duke Univ.), X. Gu (Huawei Tech.) Adaptive Board-Level Functional Fault Diagnosis Using Decision Trees F. Ye (Duke Univ.), Z. Zhang (Huawei Tech.), K. Chakrabarty (Duke Univ.), X. Gu (Huawei Tech.) Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs A. Cook, D. Ull, M. Elm, H. -J. Wunderlich (Univ. Stuttgart), H. Randoll, S. Dohren (Bosch) 13:30-15:10 Section 7A (Special Session 3) Power-Aware Testing: Present and Future Organizer: X. Wen (Kyushu Inst. Tech.) Moderator: S.M. Reddy (Univ. Iowa) Why and How Controlling Power Consumption During Test: A Survey A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel (LIRMM) PowerMAX: Fast Power Analysis during Test W. Zhao, M. Tehranipoor (Univ. Connecticut) Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network Validation P. Varma (Apache Design) Power-Supply Droop and Its Impacts on Structural At-Speed Testing X. Lin (Mentor Graphics) 13:30-15:10 Section 7B Special Session 4: Post-Silicon Measurements and Tests Regular Session: Analog Test and High Speed I/O Test II Organizer: T. J. Yamaguchi (Advantest) (Special Session) A Test Screening Method for 28nm HK/MG Single-port and Dual-port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues K. Nii, Y. Tsukamoto, Y. Ishii, M. Yabuuchi, H. Fujiwara, K. Okamoto (Renesas) Impact of All-Digital PLL on SoC Testing T. Nakura, T. Iizuka, K. Asada (Univ. Tokyo) (Regular Session) Post-Silicon Jitter Measurements K. Niitsu (Gunma Univ.), T. J. Yamaguchi, M. Ishida (Advantest), H. Kobayashi (Gunma Univ.) An Active Test Fixture Approach for Testing 28 Gbps Applications Using a Lower Data Rate ATE System J. Moreira, B. Roth, C. McCowan (Advantest) 13:30-15:10 Section 7C Panel: Board / System Test Is Componet Interconnection Test Enough for Board or System Test? Panel Moderator: E. Larsson, (Lund Univ.) Panelists: X. Gu, (Huawei Tech.) S. Kameyama, (Fujitsu) M. Keim, (Mentor Graphics) J. Qian, (AMD) K. Chakrabarty, (Duke Univ.) 15:20 Social Program Nov. 22nd, 2012 9:15-10:30 Session 8A Embedded Tutorial: Yield Analysis Diagnosis for Accelerating Yield and Failure Chair: K. S. -M. Li (National Sun Yat-sen Univ.) W. -T. Cheng (Mentor Graphics), F. -M. Kuo (TSMC) 9:15-10:30 Session 8B Built-In Test and Built-In Characterization Technique Chair: X. Li (ICT/CAS) A Scan-Out Power Reduction Method for Multi-Cycle BIST S. Wang, Y. Sato, K. Miyase, S. Kajihara (Kyushu Inst. Tech.) A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume W. -C. Lien, K. -J. Lee (National Cheng Kung Univ.), T. -Y. Hsieh (National Sun Yat-sen Univ.) A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC Y.-H. Chou, J. -L. Huang, X. -L. Huang (National Taiwan Univ.) 9:15-10:30 Session 8C ATPG Chair: Y. Higami (Ehime Univ.) Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization S. Eggersgluess (Univ. Bremen), M. Yilmaz (NVIDIA), K. Chakrabarty (Duke Univ.) Functional Pattern Generation for Asynchronous Designs in a Test Processor Environment S. Zeidler, C. Wolf, M. Krstic, R. Kraemer (IHP) Reduced-Complexity Transition-Fault Test Generation for Non-Scan Circuits through High-level Mutant Injection V. Guarnieri, F. Fummi (Univ. Verona), K. Chakrabarty (Duke Univ.) 10:50-12:05 Session 9A Yield Analysis and Enhancement Chair: S. -Y. Huang (National Tsing Hua Univ.) Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs S. -K. Lu, T. -L. Li (National Taiwan Univ.), P. Ning (Nanya Tech.) A Hybrid Flow for Memory Failure Bitmap Classification J. Li (Tsinghua Univ.), Y. Huang, W. -T. Cheng, C. Schuermyer (Mentor Graphics), D. Xiang (Tsinghua Univ.), E. Faehn (STMicroelectronics), R. Farrugia (STEricsson) Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data J. -H. Kuo, T. -S. Hsu, J. -J. Liou (National Tsing Hua Univ.) 10:50-12:05 Session 9B DFT / On-Line Test Chair: P. Bernardi (Politecnico di Torino) NoC Dynamically Reconfigurable as TAM T. Sbiai, K. Namba (Chiba Univ.) On-line Error Detection in Digital Microfluidic Biochips D. Mitra (National Institute of Technology), S. Ghoshal, H. Rahaman (Bengal Engineering & Science Univ.), K. Chakrabarty (Duke Univ.), B. B. Bhattacharya (Indian Statistical Inst.) Automatic Test Program Generation for Out-of-Order Superscalar Processors Y. Zhang, A. Rezine, P. Eles, Z. Peng (Linkoping Univ.) 10:50-12:05 Session 9C Delay and Performance Test Chair: Y. Sato (Kyushu Inst. Tech.) Variation-Aware Fault Grading A. Czutro (Univ. Freiburg), M. E. Imhot (Univ. Stuttgart), J. Jiang (Univ. Passau), A. Mumtaz (Univ. Stuttgart), M. Sauer, B. Becker (Univ. Freiburg), I. Polian (Univ. Passau), H. -J. Wunderlich (Univ. Stuttgart) On-chip Detection of Process Shift and Process Spread for Silicon Debugging and Model-Hardware Correlation I. A. K. M. Mahfuzul, H. Onodera (Kyoto Univ.) Efficient Trojan Detection via Calibration of Process Variations B. Cha, S. K. Gupta (Univ. Southern California)