Nov. 19th, 2012
9:15-12:15 Tutorial 1
Beyond DFT: The Convergence of DFM, Variability, Yield, Diagnosis and Reliability
S. Venkataraman (Intel), R. Aitken (ARM)
Summary:
The
tutorial goal is to show how design for yield (DFY) and design for
manufacturability (DFM) are tightly coupled into what we conventionally think
of as test. As process geometries shrink, the line between defects and process
variation blurs to the point where it is essentially non-existent. The basics
of yield and what fabs do to improve defectivity and manage yield are
described. DFM techniques to analyze the design content, flag areas of design that
could limit yield, and make changes to improve yield are discussed. This
tutorial will provide background needed for DFT practitioners to understand DFM
and DFY, and see how their work relates to it. The ultimate goal is to spur
attendees to conducting their own research in the area, and to apply these
concepts in their jobs.
Keyworks:
Yield, Yield Modeling, Design-for-Manufacturability, Diagnosis, Design Margin, Yield Monitors, Variability and Reliability.
13:45-16:45 Tutorial 2
Power-Aware Testing and Test Strategies for Low Power Devices
P. Girard (LIRMM), N. Nicolici (McMaster Univ.), X. Wen (Kyushu Inst. Tech.)
Summary:
Managing the power consumption of circuits and systems is now considered
as one of the most important challenges for the semiconductor industry.
Elaborate power management strategies, such as voltage scaling, clock gating
or power gating techniques, are used today to control the power dissipation
during functional operation. The usage of these strategies has various
implications on manufacturing test, and power-aware test is therefore increasingly
becoming a major consideration during design-for-test and test preparation
for low power devices. This tutorial provides knowledge in this area. It
is organized into three main parts. The first one gives necessary background
and discusses issues arising from excessive power dissipation during test
application. The second part provides comprehensive knowledge of structural
and algorithmic solutions that can be used to alleviate such problems.
The last part surveys low power design techniques and shows how these low
power devices can be tested safely without affecting yield and reliability.
EDA solutions for considering power during test and design-for-test are
also discussed in the last part of the tutorial.
Keyworks:
Power-aware Testing, Power-Constrained Testing, Low Power Design, Power
Management, Test Power Issues, Design-for-Test, Scan Testing, Built-In
Self-Test, Test Data Compression, ATPG
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The 21st Asian Test Symposium