|Track A||Track B||Track C|
|Mon Nov 21st||8:30||Registration Desk Open|
|9:15||Tutorial 1: Industrial Advancements in Diagnosis Driven Yield Analysis|
|13:45||Tutorial 2: Combining Structural and Functional Test Approaches Across System Levels|
|Tue Nov 22nd||8:00||Registration Desk Open|
|9:00||Opening and Awards
Keynote: Embracing Failures
Special Plenary in Honor of Prof. Edward J. McCluskey
|11:15||Invited Talk 1: Quality and Reliability Challenges in Internet of Things
Invited Talk 2: Secure Value Chain Enablement with Smart-Connected SoCs
|14:30||1A: Delay Test and Simulation||1B: Fault Diagnosis, Debug and Verification||1C: Hardware Security|
|16:30||2A: Special Session 1: Test and Reliability Issues in 2.5D and 3D Integration||2B: Analog and Mixed-Signal Test||2C: Scan Test|
|Wed Nov 23rd||8:00||Registration Desk Open|
|9:00||3A: Industry Session Presentations||3B: Special Session 2: Doctoral Thesis Contest Presentations||3C: Fault Diagnosis|
|10:25||4A: Special Session 3: Industry Posters, Doctoral Thesis Contest Posters|
|10:45||4B: Fault Modeling||4C: Power-aware Test|
|13:00||5A: Automatic Test Pattern Generation||5B: Built-In Self-Test||5C: 3D IC Testing|
|14:30||25th Anniversary Panel: "Past, Present and Future of ATS"|
|17:00||25th Anniversary Social Program|
|Thu Nov 24th||8:00||Registration Desk Open|
|9:00||6A: Special Session 4: Managing Reliability of Integrated Circuits: Lifetime Metering and Design for Healing||6B: Fault Tolerance||6C: Analog Circuits and High-Speed I/O Test|
|10:35||7A: Memory Test and Reliability||7B: Dependable Systems|
Yu HUANG - Mentor Graphics
Wu YANG - Mentor Graphics
Wu-Tung CHENG - Mentor Graphics
Delivering a stable high yield product on time is the ultimate goal for the semiconductor industry. With the increasing complexity of design and processes, too often, the yield is lower than expected or takes longer to ramp to the target level. Scan diagnosis driven yield analysis (DDYA) can expedite the debug and analysis process reducing the time-to-market and minimizing the related cost. Identifying systematic defects, understanding the root causes of the systematic defect and selecting the right die and suspect candidate for physical failure analysis (PFA) are important components for yield analysis. The recent technology advances in scan chain diagnosis, layout-aware and cell-aware diagnosis can provide fast, high resolution and accurate volume diagnosis data used in the aforementioned steps. Based on volume diagnosis results, different analysis techniques are developed to help identify the systematic defects. These methodologies include the systematic suspect location analysis, wafer zonal analysis, design-for-manufacturing (DFM) correlation analysis, root-cause deconvolution (RCD) and others. RCD is a statistical analysis method utilizing Bayesian model. It calculates the defect weight probability with the design information and diagnosis results. It provides a direct or visual defect distribution pareto based on maximum likelihood and further helps drill down to the correspondent die and suspect for each root cause, which can be used for PFA. In this DDYA solution, the PFAs on the selected die and suspect candidates are to validate the findings on the systematic root causes. Hence it greatly reduces the efforts, costs and time for yield analysis. The tutorial will review the recent industrial advancements in the above three areas and each topic will be covered for about 50 minutes.
Artur JUTMAN - Tallinn University of Technology
Hans-Joachim WUNDERLICH - University of Stuttgart
Matteo SONZA REORDA - Politecnico di Torino
This tutorial introduces into the best practices, current challenges and advanced techniques of high-quality system-level test and diagnosis. Specialized techniques and industrial standards of testing complex systems (which may correspond to a system-on-chip, board or interconnected system) are introduced. The reuse for system test of design-for-test structures and test data developed at module level is discussed, including the limitations and research challenges. Structural test methods have to be complemented by functional methods; hence, state-of-the-art and leading edge research for functional testing are covered. Solutions change depending on the scenario (manufacturing test or in-field test) and the goal (test or diagnosis). The tutorial also discusses the role of standards and regulations in the area.
John M. CARULLI Jr - GLOBALFOUNDRIES, USA
For advanced CMOS technologies, we are now capable of creating billions of transistors per design. Following the economic path of Moore's law, we have integrated new materials at an increasing pace to drive performance, power, and reliability. As layout features went sub-lithography, we have built expertise to fool light. We are integrating vertically with 2.5D/3D packaging. There is research building around monolithic 3D. These advances brought and are continuing to bring significant challenges in dealing with variation. Designers have been managing variation by using adaptive circuit and system approaches for some time. Essentially they have been enabling the design to adapt and accommodate the process capability. This presentation will explore what is a failure in the context of increasing variation and adapting designs and resilient systems. This discussion should challenge assumptions and provoke conversations in testing approaches to economically meet a wide range of market segment requirements.
John M. Carulli Jr leads the Test organization at GLOBALFOUNDRIES Fab8 in Malta, NY working on leading edge CMOS technologies. He previously had 21 years at Texas Instruments where he was a Distinguished Member of the Technical Staff. While in the Analog Engineering Operations organization he led test and design data mining methods targeted at test cost reduction. Prior to that in the Silicon Technology Development organization, he was the Manager of the Product Reliability group responsible for product and design reliability activities for new technology development.
John holds 7 US Patents. He has over 50 publications in the areas of reliability, test, and process development. He is co-recipient of two Best Paper Awards and two Best Paper Nominations working in close collaboration with university partners. John serves on the organizing or program committees of several conferences including the International Test Conference, VLSI Test Symposium, and European Test Symposium. He was a recipient of the SRC 2010 Mahboob Khan Outstanding Industry Liaison Award for student mentoring and research collaboration. He is a Senior Member of IEEE. He received his B.S.E.E. and M.S.E.E. degrees from the University of Vermont in Burlington, VT. His research interests include product reliability, outlier analysis, machine learning, performance modeling, logic diagnosis, and security.
Chair: James Chien-Mo LI - National Taiwan University
Cheng-Wen WU - National Tsing Hua University, Taiwan
The global semiconductor business over the past thirty years shows an encouraging trend of growth in general, with only a few glitches that did not hinder the long-term trend. The growing trend, however, slows down in recent years, along with the global economy. Meanwhile, the Internet-of-Things (IOT) has long been identified, or expected, as the main driving force of growth for many industries in the future, if not now. Unfortunately, so far there is not so much evidence that IOT will likely give a great boost to the semiconductor industry (that we are all concerned here) in the near future. People are realizing that IOT is NOT a tangible industry, but instead just a phenomenon or notion of industry migration toward smart and connected everything. If IOT is going to be the savior of the struggling semiconductor industry, what will be the key factors of its success? In my speech, in addition to paying my respects to Prof. Ed McCluskey, I will address this issue and propose the Symbiotic System Model (SSM) for developing IOT devices and systems. Especially for device and system test, the Symbiosis-Based Test (SBT) will also be proposed. A Symbiotic Relationship (SR) is a relationship of mutual dependence between two different (biological or electronic) systems, where (part of) one system’s input is from the other’s output, and vice versa. A Symbiotic System (SS) (see Fig. 1) is a twin system comprising the primary (functional) system and secondary (test) system, with SR. A couple of cases of SSMs for existing and/or future applications will be demonstrated, e.g., an IOT-based sensor network that is connected to cloud with big data analytics for natural disaster prevention, a data center storage system with at least tens of thousands of nodes that should be optimized for energy efficiency and lifetime, a heterogeneous network of computing nodes in a data center or a distributed environment that should be optimized for cost, performance and lifetime, an enhanced cellular automata where cells are equipped with sensors, etc. This speech is meant for triggering more research activities regarding establishing a sound IOT platform that allows heterogeneous integration of technologies and partners to migrate certain industries based on the notion of IOT.
Cheng-Wen Wu received the BSEE degree from National Taiwan University in 1981, and the MS and PhD degrees in ECE from UCSB in 1985 and 1987, respectively. Since 1988, he has been with the Department of EE, National Tsing Hua University (NTHU), Hsinchu, Taiwan, where he is currently a Tsing Hua Distinguished Chair Professor. He has served in the past at NTHU as the Director of Computer Center, Chair of EE Department, Director of IC Design Technology Center, Dean of the College of EECS, and Senior Vice President for Research. When he was on leave from NTHU from 2007 to 2014, he served at ITRI as the General Director of the SOC Technology Center, and the Vice President and General Director of the Information and Communications Labs. Dr. Wu received the Academic Award from the Ministry of Education (MOE) in 2005. He became a Golden Core Member of the IEEE Computer Society in 2006. In 2013, he received the National Endowed Chair Professorship from MOE, and in 2015, he received the EE Medal (highest honor) from the Chinese Institute of Electrical Engineers (CIEE). His research interests include design and test of high performance VLSI circuits and systems, and test and repair of semiconductor memory. He is a life member of the CIEE, a life member of Taiwan IC Design Society, and a Fellow of the IEEE.
Masahiro Fujita - University of Tokyo, Japan
Masahiro Fujita received his Ph.D. in Information Engineering from the University of Tokyo in 1985 on his work on model checking of hardware designs. From 1993 to 2000, he was director at Fujitsu Laboratories of America and headed a hardware formal verification group. Since March 2000, he has been a professor at VLSI Design and Education Center of the University of Tokyo. He has done innovative work in the areas of hardware verification, synthesis, testing, and software verification-mostly targeting embedded software and web-based programs. He has authored and co-authored 10 books, and has more than 300 publications. He has been involved as program and steering committee member in many prestigious conferences on CAD, VLSI designs, software engineering, and more. His current research interests include synthesis and verification in SoC (System on Chip), hardware/software co-designs targeting embedded systems, digital/analog co-designs, and formal analysis, verification, and synthesis of cyber physical systems.
Adit Singh - Auburn University, USA
Adit D. Singh is James B. Davis Professor of Electrical and Computer Engineering at Auburn University, USA. Before joining Auburn in 1991, he served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over two hundred research papers, lectured widely all over the world, and served as a consultant to several semiconductor companies. He has also served as an expert witness in major patent litigation cases, and is himself a co-inventor on international patents that have been licensed to industry. He has had leadership roles as General Chair/Co-Chair/Program Chair for dozens of international VLSI design and test conferences and also on the editorial boards of several journals, including IEEE Design and Test and JETTA. Singh is a past Chair of the IEEE Test Technology Technical Council (TTTC), and has also served on the Board of Governors of the IEEE Council on Design Automation (CEDA). He is a Fellow of IEEE and a Golden Core member of the IEEE Computer Society.
James Chien-Mo Li - National Taiwan University
James Chien-Mo Li received his BSEE degree in 1993 from National Taiwan University, Taipei, Taiwan. He received his MSEE and PhD degrees in electrical engineering from Stanford University in 1997 and 2002 respectively. His PhD advisor is Professor McCluskey. He is currently a professor of Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan. His research interest includes test generation, low power testing, and diagnosis. He has coauthored three books in EDA and testing.
Hans-Joachim Wunderlich - University of Stuttgart, Germany
Hans-Joachim Wunderlich is a full professor and the director of the Institute of Computer Architecture and Computer Engineering at the University of Stuttgart. He studied Mathematics and Philosophy at the Universities of Konstanz and Freiburg, Germany, and received his PhD degree (Dr. rer. nat.) from the University of Karlsruhe in 1986. Since then, he has worked as a professor at the universities of Karlsruhe, Duisburg, Siegen and Stuttgart. For more than 32 years, Prof. Wunderlich contributed to the areas of VLSI testing, Design for Test, Dependability, Fault Tolerance and Design Automation. He published more than 250 books and articles in these fields, and led numerous projects funded by industry, European Commission, German government or national funding organizations like DFG. Prof. Wunderlich was recipient of the award for excellent academic teaching of the state of Baden-Württemberg, was promoted Golden Core Member of the IEEE Computer Society, and was elevated Fellow of the IEEE.
Yervant ZORIAN - Chief Architect and Fellow at Synopsys, USA
With continuous growth in the Internet of Things (IoT), it is estimated that over 30 billion IoT devices will ship by 2020. The ability to sense countless amounts of information that communicates to the cloud is driving innovation into IoT applications, such as in wearable devices (for health, fitness or infotainment applications), in automotive systems and in machine-to-machine applications (in smart appliances, smart cities or commerce). It has become crucial for today’s IoT chips to use a range of new solutions during the design stage to ensure manufacturing quality, field reliability and security. DFT designers need to use new test and reliability solutions to enable power reductions during test, concurrent test, isolated debug and diagnosis, pattern porting, calibration, and uniform access. Moreover, the per unit IoT price remains a key factor in high volume production. Thus, minimizing the test cost while meeting the above technical challenges is one of the major challenges of the IoT industry. This invited talk, besides discussing the key trends and challenges of IoT, will cover solutions to handle the wide range of potential robustness challenges during all periods of the IoT lifecycle from design, post silicon bring-up, volume production, to in-system operation.
Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of several symposia and workshops. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science.
Michael CHEN - Director, Design for Security, New Ventures Division, Mentor Graphics Corporation, USA
Mentor Graphics is developing a secure end-to-end platform that enables SoC Suppliers to establish inborn hardware root-of-trust, and provide anti-reverse engineering protection. Solution creates unique fingerprint on every die, securely register Chip ID’s into operations server and authenticate SoCs in the supply chain to monitor usage, securely configure IPs, enabling multi-debug modes, and establishing layered security. As a result, connected SoC suppliers will be able to provision SoC features and SKUs anywhere in the value chain and can gather analytics on field use to reduce field failures and provide secure field updates.
A twenty-five year veteran at Mentor Graphics, Michael Chen is currently a Business Unit Director in the New Ventures Division. As such, Michael manages leading-edge technology efforts for the company’s Design for Security platform. Michael is invited often to talk about designing security and secure IC supply chain. He has presented at conferences such as GOMACTech, IEEE VLSI Test Symposium, CHASE (Center for Hardware Assurance, Security, & Engineering) conference, SEMICon West, and the Design Automation Conference where he chaired a special session on “Who is the biggest threat to tomorrow’s security?” He currently serves as Chair of the Trustworthy and Secure Semiconductors and Systems (T3S) TAB committee with Semiconductor Research Corporation (SRC) and collaboration with National Science Foundation. He holds several patents.
Chair: Ilia POLIAN - University of Passau, Germany
Chair: Maksim JENIHHIN - Tallinn University of Technology, Estonia
Chair: Michael CHEN - Mentor Graphics Corporation, USA
Mehdi TAHOORI - Karlsruhe Institute of Technology, Germany
Krishnendu CHAKRABARTY - Duke University, USA
Chair: Rimon IKENO - The University of Tokyo, Japan
Chair: Yu HUANG - Mentor Graphics Co., USA
Chair: Toru NAKURA - The University of Tokyo, Japan
Chair: Xinli GU - Futurewei Tech. Inc. (Huawei in USA), USA
Chair: Virendra SINGH - Indian Institute of Technology Bombay, India
Chair: Michael A. KOCHTE - University of Stuttgart, Germany
Chair: Stephan EGGERSGLÜß - University of Bremen, Germany
Chair: Hiroyuki YOTSUYANAGI - Tokushima University, Japan
Chair: Jin-Fu LI - National Central University, Taiwan
|Chair:||Cheng-Wen Wu - National Tsing Hua University|
|Panelists:||Hideo Fujiwara - Osaka Gakuin University, Japan|
|Yervant Zorian - Synopsys, Inc.|
|Xiaowei Li - Chinese Academy of Sciences, Beijing|
|Kuhn-Jong Lee - National Cheng Kung University, Tainan, Taiwan|
|Seiji Kajihara, Kyushu Institute of Technology, Fukuoka, Japan|
Krishnendu Chakrabarty, Duke University, NC, U.S.A.
Organizer: Sandip KUNDU - University of Massachusetts, Amherst, USA
Chair: Jaan RAIK - Tallinn University of Technology, Estonia
Chair: Jiun-Lang HUANG - National Taiwan University, Taiwan
Chair: Huawei LI - Institute of Computing Technology, CAS, China
Chair: Hans G. KERKHOFF - University of Twente, Netherland