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Advance Program

Tutorial 1: Industrial Advancements in Diagnosis Driven Yield Analysis

Yu HUANG - Mentor Graphics
Wu YANG - Mentor Graphics
Wu-Tung CHENG - Mentor Graphics

Delivering a stable high yield product on time is the ultimate goal for the semiconductor industry. With the increasing complexity of design and processes, too often, the yield is lower than expected or takes longer to ramp to the target level. Scan diagnosis driven yield analysis (DDYA) can expedite the debug and analysis process reducing the time-to-market and minimizing the related cost. Identifying systematic defects, understanding the root causes of the systematic defect and selecting the right die and suspect candidate for physical failure analysis (PFA) are important components for yield analysis. The recent technology advances in scan chain diagnosis, layout-aware and cell-aware diagnosis can provide fast, high resolution and accurate volume diagnosis data used in the aforementioned steps. Based on volume diagnosis results, different analysis techniques are developed to help identify the systematic defects. These methodologies include the systematic suspect location analysis, wafer zonal analysis, design-for-manufacturing (DFM) correlation analysis, root-cause deconvolution (RCD) and others. RCD is a statistical analysis method utilizing Bayesian model. It calculates the defect weight probability with the design information and diagnosis results. It provides a direct or visual defect distribution pareto based on maximum likelihood and further helps drill down to the correspondent die and suspect for each root cause, which can be used for PFA. In this DDYA solution, the PFAs on the selected die and suspect candidates are to validate the findings on the systematic root causes. Hence it greatly reduces the efforts, costs and time for yield analysis. The tutorial will review the recent industrial advancements in the above three areas and each topic will be covered for about 50 minutes.

Tutorial 2: Combining Structural and Functional Test Approaches Across System Levels

Artur JUTMAN - Tallinn University of Technology
Hans-Joachim WUNDERLICH - University of Stuttgart
Matteo SONZA REORDA - Politecnico di Torino

This tutorial introduces into the best practices, current challenges and advanced techniques of high-quality system-level test and diagnosis. Specialized techniques and industrial standards of testing complex systems (which may correspond to a system-on-chip, board or interconnected system) are introduced. The reuse for system test of design-for-test structures and test data developed at module level is discussed, including the limitations and research challenges. Structural test methods have to be complemented by functional methods; hence, state-of-the-art and leading edge research for functional testing are covered. Solutions change depending on the scenario (manufacturing test or in-field test) and the goal (test or diagnosis). The tutorial also discusses the role of standards and regulations in the area.

Opening and Awards

Opening Keynote: Embracing Failures

John M. CARULLI Jr - GLOBALFOUNDRIES, USA

For advanced CMOS technologies, we are now capable of creating billions of transistors per design. Following the economic path of Moore's law, we have integrated new materials at an increasing pace to drive performance, power, and reliability. As layout features went sub-lithography, we have built expertise to fool light. We are integrating vertically with 2.5D/3D packaging. There is research building around monolithic 3D. These advances brought and are continuing to bring significant challenges in dealing with variation. Designers have been managing variation by using adaptive circuit and system approaches for some time. Essentially they have been enabling the design to adapt and accommodate the process capability. This presentation will explore what is a failure in the context of increasing variation and adapting designs and resilient systems. This discussion should challenge assumptions and provoke conversations in testing approaches to economically meet a wide range of market segment requirements.

John M. Carulli Jr leads the Test organization at GLOBALFOUNDRIES Fab8 in Malta, NY working on leading edge CMOS technologies. He previously had 21 years at Texas Instruments where he was a Distinguished Member of the Technical Staff. While in the Analog Engineering Operations organization he led test and design data mining methods targeted at test cost reduction. Prior to that in the Silicon Technology Development organization, he was the Manager of the Product Reliability group responsible for product and design reliability activities for new technology development.

John holds 7 US Patents. He has over 50 publications in the areas of reliability, test, and process development. He is co-recipient of two Best Paper Awards and two Best Paper Nominations working in close collaboration with university partners. John serves on the organizing or program committees of several conferences including the International Test Conference, VLSI Test Symposium, and European Test Symposium. He was a recipient of the SRC 2010 Mahboob Khan Outstanding Industry Liaison Award for student mentoring and research collaboration. He is a Senior Member of IEEE. He received his B.S.E.E. and M.S.E.E. degrees from the University of Vermont in Burlington, VT. His research interests include product reliability, outlier analysis, machine learning, performance modeling, logic diagnosis, and security.

Special Plenary in Honor of Prof. Edward J. McCluskey

Chair: James Chien-Mo LI - National Taiwan University

Keynote: Symbiotic-System Approach for IOT Devices

Cheng-Wen WU - National Tsing Hua University, Taiwan

The global semiconductor business over the past thirty years shows an encouraging trend of growth in general, with only a few glitches that did not hinder the long-term trend. The growing trend, however, slows down in recent years, along with the global economy. Meanwhile, the Internet-of-Things (IOT) has long been identified, or expected, as the main driving force of growth for many industries in the future, if not now. Unfortunately, so far there is not so much evidence that IOT will likely give a great boost to the semiconductor industry (that we are all concerned here) in the near future. People are realizing that IOT is NOT a tangible industry, but instead just a phenomenon or notion of industry migration toward smart and connected everything. If IOT is going to be the savior of the struggling semiconductor industry, what will be the key factors of its success? In my speech, in addition to paying my respects to Prof. Ed McCluskey, I will address this issue and propose the Symbiotic System Model (SSM) for developing IOT devices and systems. Especially for device and system test, the Symbiosis-Based Test (SBT) will also be proposed. A Symbiotic Relationship (SR) is a relationship of mutual dependence between two different (biological or electronic) systems, where (part of) one system’s input is from the other’s output, and vice versa. A Symbiotic System (SS) (see Fig. 1) is a twin system comprising the primary (functional) system and secondary (test) system, with SR. A couple of cases of SSMs for existing and/or future applications will be demonstrated, e.g., an IOT-based sensor network that is connected to cloud with big data analytics for natural disaster prevention, a data center storage system with at least tens of thousands of nodes that should be optimized for energy efficiency and lifetime, a heterogeneous network of computing nodes in a data center or a distributed environment that should be optimized for cost, performance and lifetime, an enhanced cellular automata where cells are equipped with sensors, etc. This speech is meant for triggering more research activities regarding establishing a sound IOT platform that allows heterogeneous integration of technologies and partners to migrate certain industries based on the notion of IOT.

Cheng-Wen Wu received the BSEE degree from National Taiwan University in 1981, and the MS and PhD degrees in ECE from UCSB in 1985 and 1987, respectively. Since 1988, he has been with the Department of EE, National Tsing Hua University (NTHU), Hsinchu, Taiwan, where he is currently a Tsing Hua Distinguished Chair Professor. He has served in the past at NTHU as the Director of Computer Center, Chair of EE Department, Director of IC Design Technology Center, Dean of the College of EECS, and Senior Vice President for Research. When he was on leave from NTHU from 2007 to 2014, he served at ITRI as the General Director of the SOC Technology Center, and the Vice President and General Director of the Information and Communications Labs. Dr. Wu received the Academic Award from the Ministry of Education (MOE) in 2005. He became a Golden Core Member of the IEEE Computer Society in 2006. In 2013, he received the National Endowed Chair Professorship from MOE, and in 2015, he received the EE Medal (highest honor) from the Chinese Institute of Electrical Engineers (CIEE). His research interests include design and test of high performance VLSI circuits and systems, and test and repair of semiconductor memory. He is a life member of the CIEE, a life member of Taiwan IC Design Society, and a Fellow of the IEEE.

Tribute: Pioneer in reliable/dependable digital electronic systems

Masahiro Fujita - University of Tokyo, Japan

Masahiro Fujita received his Ph.D. in Information Engineering from the University of Tokyo in 1985 on his work on model checking of hardware designs. From 1993 to 2000, he was director at Fujitsu Laboratories of America and headed a hardware formal verification group. Since March 2000, he has been a professor at VLSI Design and Education Center of the University of Tokyo. He has done innovative work in the areas of hardware verification, synthesis, testing, and software verification-mostly targeting embedded software and web-based programs. He has authored and co-authored 10 books, and has more than 300 publications. He has been involved as program and steering committee member in many prestigious conferences on CAD, VLSI designs, software engineering, and more. His current research interests include synthesis and verification in SoC (System on Chip), hardware/software co-designs targeting embedded systems, digital/analog co-designs, and formal analysis, verification, and synthesis of cyber physical systems.

Tribute: What I have learned from Professor EdMcCluskey

Adit Singh - Auburn University, USA

Adit D. Singh is James B. Davis Professor of Electrical and Computer Engineering at Auburn University, USA. Before joining Auburn in 1991, he served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over two hundred research papers, lectured widely all over the world, and served as a consultant to several semiconductor companies. He has also served as an expert witness in major patent litigation cases, and is himself a co-inventor on international patents that have been licensed to industry. He has had leadership roles as General Chair/Co-Chair/Program Chair for dozens of international VLSI design and test conferences and also on the editorial boards of several journals, including IEEE Design and Test and JETTA. Singh is a past Chair of the IEEE Test Technology Technical Council (TTTC), and has also served on the Board of Governors of the IEEE Council on Design Automation (CEDA). He is a Fellow of IEEE and a Golden Core member of the IEEE Computer Society.

Tribute: Professor McCluskey, a great researcher and educator

James Chien-Mo Li - National Taiwan University

James Chien-Mo Li received his BSEE degree in 1993 from National Taiwan University, Taipei, Taiwan. He received his MSEE and PhD degrees in electrical engineering from Stanford University in 1997 and 2002 respectively. His PhD advisor is Professor McCluskey. He is currently a professor of Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan. His research interest includes test generation, low power testing, and diagnosis. He has coauthored three books in EDA and testing.

Tribute: Learning how to teach

Hans-Joachim Wunderlich - University of Stuttgart, Germany

Hans-Joachim Wunderlich is a full professor and the director of the Institute of Computer Architecture and Computer Engineering at the University of Stuttgart. He studied Mathematics and Philosophy at the Universities of Konstanz and Freiburg, Germany, and received his PhD degree (Dr. rer. nat.) from the University of Karlsruhe in 1986. Since then, he has worked as a professor at the universities of Karlsruhe, Duisburg, Siegen and Stuttgart. For more than 32 years, Prof. Wunderlich contributed to the areas of VLSI testing, Design for Test, Dependability, Fault Tolerance and Design Automation. He published more than 250 books and articles in these fields, and led numerous projects funded by industry, European Commission, German government or national funding organizations like DFG. Prof. Wunderlich was recipient of the award for excellent academic teaching of the state of Baden-Württemberg, was promoted Golden Core Member of the IEEE Computer Society, and was elevated Fellow of the IEEE.

Invited Talk 1: Quality and Reliability Challenges in Internet of Things

Yervant ZORIAN - Chief Architect and Fellow at Synopsys, USA

With continuous growth in the Internet of Things (IoT), it is estimated that over 30 billion IoT devices will ship by 2020. The ability to sense countless amounts of information that communicates to the cloud is driving innovation into IoT applications, such as in wearable devices (for health, fitness or infotainment applications), in automotive systems and in machine-to-machine applications (in smart appliances, smart cities or commerce). It has become crucial for today’s IoT chips to use a range of new solutions during the design stage to ensure manufacturing quality, field reliability and security. DFT designers need to use new test and reliability solutions to enable power reductions during test, concurrent test, isolated debug and diagnosis, pattern porting, calibration, and uniform access. Moreover, the per unit IoT price remains a key factor in high volume production. Thus, minimizing the test cost while meeting the above technical challenges is one of the major challenges of the IoT industry. This invited talk, besides discussing the key trends and challenges of IoT, will cover solutions to handle the wide range of potential robustness challenges during all periods of the IoT lifecycle from design, post silicon bring-up, volume production, to in-system operation.

Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of several symposia and workshops. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science.

Invited Talk 2: Secure Value Chain Enablement with Smart-Connected SoCs

Michael CHEN - Director, Design for Security, New Ventures Division, Mentor Graphics Corporation, USA

Mentor Graphics is developing a secure end-to-end platform that enables SoC Suppliers to establish inborn hardware root-of-trust, and provide anti-reverse engineering protection. Solution creates unique fingerprint on every die, securely register Chip ID’s into operations server and authenticate SoCs in the supply chain to monitor usage, securely configure IPs, enabling multi-debug modes, and establishing layered security. As a result, connected SoC suppliers will be able to provision SoC features and SKUs anywhere in the value chain and can gather analytics on field use to reduce field failures and provide secure field updates.

A twenty-five year veteran at Mentor Graphics, Michael Chen is currently a Business Unit Director in the New Ventures Division. As such, Michael manages leading-edge technology efforts for the company’s Design for Security platform. Michael is invited often to talk about designing security and secure IC supply chain. He has presented at conferences such as GOMACTech, IEEE VLSI Test Symposium, CHASE (Center for Hardware Assurance, Security, & Engineering) conference, SEMICon West, and the Design Automation Conference where he chaired a special session on “Who is the biggest threat to tomorrow’s security?” He currently serves as Chair of the Trustworthy and Secure Semiconductors and Systems (T3S) TAB committee with Semiconductor Research Corporation (SRC) and collaboration with National Science Foundation. He holds several patents.

Session 1A: Delay Test and Simulation

Chair: Ilia POLIAN - University of Passau, Germany

• X Marks the Spot: Clustering Scan-Flip-Flops for Faster-than-at-Speed Test
  Matthias KAMPMANN, Sybille HELLEBRAND (University of Paderborn)
• Crypt-Delay: Encrypting IP Cores with Capabilities for Gate-level Logic and Delay Simulations
  Parameswaran RAMANATHAN, Kewal SALUJA (University of Wisconsin - Madison)
• On the Switching Activity in Faulty Circuits During Test Application
  Irith POMERANZ (Purdue University), Sudhakar REDDY (University of Iowa)
• Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test
  Stefan HOLST, Xiaoqing WEN, Seiji KAJIHARA (Kyushu Institute of Technology), Eric SCHNEIDER, Michael KOCHTE (University of Stuttgart), Yuta YAMATO (Nara Institute of Science and Technology), Hans-Joachim WUNDERLICH (University of Stuttgart)

Session 1B: Fault Diagnosis, Debug and Verification

Chair: Maksim JENIHHIN - Tallinn University of Technology, Estonia

• Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis
  Sheng-Lin LIN, Cheng-Hung WU, Kuen Jong LEE (National Cheng Kung University)
• A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality
  Amir Masoud GHAREHBAGHI, Masahiro FUJITA (University of Tokyo)
• A Verification guided approach for selective program transformations for Approximate Computing
  Sayandeep MITRA (Indian Statistical Institute), Moumita DAS (Meghnad Saha Institute of Technology), Ansuman BANERJEE (Indian Statistical Institute), Kausik DATTA (Mentor Graphics), Tsung-Yi HO (National Tsing Hua University)
• Property Coverage Analysis based Trustworthiness Verification for Potential threats from EDA tools
  Yingxin QIU, Huawei LI, Xiaowei LI (Institute of Computing Technology, CAS)

Session 1C: Hardware Security

Chair: Michael CHEN - Mentor Graphics Corporation, USA

• Efficient Attack on Non-Linear Current Mirror PUF with Genetic Algorithm
  Qingli GUO, Jing YE, Yue GONG, Yu HU, Xiaowei LI (Institute of Computing Technology, CAS)
• Noise-Resilient SRAM Physically Unclonable Function Design for Security
  Sujay PANDEY, Sabyasachi DEYATI (Georgia Institute of Technology), Adit SINGH (Auburn University), Abhijit CHATTERJEE (Georgia Institute of Technology)
• On Test Points Enhancing Hardware Security
  Justyna ZAWADA (Poznan University of Technology), Elham MOGHADDAM, Nilanjan MUKHERJEE, Janusz RAJSKI (Mentor Graphics), Jerzy TYSZER (Poznan University of Technology)
• Side-Channel Attack on Flipped Scan Chains
  Sying-Jyan WANG, Ting-Jui CHOI (National Chung-Hsing University), Katherine Shu-Min LI (National Sun Yat-Sen University)

Session 2A: Special Session 1: Test and Reliability Issues in 2.5D and 3D Integration

Organizers:
Mehdi TAHOORI - Karlsruhe Institute of Technology, Germany
Krishnendu CHAKRABARTY - Duke University, USA

• Testing of Interposer-Based 2.5D Integrated Circuits: Challenges and Solutions
  Ran WANG (NVIDIA Corporation), Krishnendu CHAKRABARTY (Duke University)
• Pre-bond and Post-bond Testing of TSVs and Die-to-Die Interconnects
  Shi-Yu HUANG (National Tsing Hua University)
• Multicast Test Architecture and Test Scheduling for Interposer-based 2.5D ICs
  Shengcheng WANG (Karlsruhe Institute of Technology), Ran WANG (NVIDIA Corporation), Krishnendu CHAKRABARTY (Duke University), Mehdi B. TAHOORI (Karlsruhe Institute of Technology)

Session 2B: Analog and Mixed-Signal Test

Chair: Rimon IKENO - The University of Tokyo, Japan

• A Study on the Transfer Function Based Analog Fault Model for Linear and Time-Invariant Continuous-Time Analog Circuits
  Hao-Chiao HONG, Long-Yi LIN (National Chiao Tung University)
• Concurrent Stimulus and Defect Magnitude Optimization for Detection of Weakest Shorts and Opens in Analog Circuits
  Barry MULDREY, Sabyasachi DEYATI, Abhijit CHATTERJEE (Georgia Institute of Technology)
• Model-Free Testing of Analog Circuits
  Mehrdad HEYDARZADEH, Hao LUO, Mehrdad NOURANI (University of Texas at Dallas)

Session 2C: Scan Test

Chair: Yu HUANG - Mentor Graphics Co., USA

• Scan Chain Adaptation Through ECO
  Shalini PATHAK (STMicroelectronics Pvt Ltd), Jasvir SINGH (Intel), Anuj GROVER (STMicroelectronics), Mausumi POHIT, Anurag Singh BAGHEL, Gurjit KAUR (Gautam Buddha Univeristy)
• Test Strategies for Reconfigurable Scan Networks
  Michael KOCHTE, Rafał BARANOWSKI, Marcel SCHAAL, Hans-Joachim WUNDERLICH (University of Stuttgart)
• Test Time Minimization in Reconfigurable Scan Networks
  Riccardo CANTORO, Marco PALENA, Paolo PASINI, Matteo SONZA REORDA (Politecnico di Torino)

Session 3A: Industry Session

Chair: Toru NAKURA - The University of Tokyo, Japan

• Rectangular Waveform Generation With Harmonics Suppression
  Masayuki KAWABATA, Koji ASAMI (Advantest), Shohei SHIBUYA, Tomonori YANAGIDA, Haruo KOBAYASHI (Gunma University)
• Achieving Acceptable Bit Error Rate for 40 Gbps Link Using Signal Conditioning Techniques
  Jayalaxmi SATISHKUMAR, Nagesh VAIDYA (C-DAC)
• Design and Implementation of EMIB Testing on 2.5D FPGA Transceiver
  Lai Pheng TAN, Shen Shen LEE, Kian Hui WONG (Intel)
• Application of Data Mining Based Scan Diagnosis Yield Analysis in a Foundry and Fabless Working Environment
  Hao SHEN (HiSilicon Semicondutor), Lance SHEN , Pierce XU (SMIC), Wu YANG, Junna ZHONG (Mentor Graphics)
• rosTest: Universal Test Framework for Real-Time Operating System
  Siaw Chen LEE, Ong Soon EE (Intel Microelectonic)
• An optical/electrical test system for 100Gb/s optical interconnection devices for high volume production
  Takeshi MIZUSHIMA, Kazuki SHIRAHATA, Tasuku FUJIBE, Hidenobu MATSUMURA, Daisuke WATANABE, Hiroyuki MINEO (Advantest), Shin MASUDA (Advantest Laboratories)
• Multi-configuration Scan Structure for Various Purposes
  Hiroyuki IWATA, Jun MATSUSHIMA (Renesas System Design)
• End-to-End Test & Yield Solution
  Akio NAKAMURA, Ikumi OKANO, Yervant ZORIAN (Synopsys)

Session 3B: Special Session 2: Doctoral Thesis Contest Presentations

Session 3C: Fault Diagnosis

Chair: Xinli GU - Futurewei Tech. Inc. (Huawei in USA), USA

• On Achieving Maximal Chain Diagnosis Resolution Through Test Pattern Selection
  Xijiang LIN (Mentor Graphics), Sudhakar REDDY (University of Iowa), Wu-Tung CHENG (Mentor Graphics)
• A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction
  Enamul AMYEEN (Intel), Irith POMERANZ (Purdue University), Srikanth VENKATARAMAN (Intel)
• A Neural-Network-Based Fault Classifier
  Laura RODRIGUEZ GOMEZ, Hans-Joachim WUNDERLICH (University of Stuttgart)

Session 4A: Special Session 3: Poster Presentations

• Industry Session (Poster Presentation)
• Doctoral Thesis Contest (Poster Presentation)

Session 4B: Fault Modeling

Chair: Virendra SINGH - Indian Institute of Technology Bombay, India

• High-Throughput Transistor-Level Fault Simulation on GPUs
  Eric SCHNEIDER, Hans-Joachim WUNDERLICH (University of Stuttgart)
• Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test
  Hsuan-Wei LIU, Cheng-Wen WU (National Tsing Hua University)
• Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D Network-on-Chip Systems
  Khanh DANG, Michael MEYER, Yuichi OKUYAMA, Abderazek BEN ABDALLAH (University of Aizu)

Session 4C: Power-aware Test

Chair: Michael A. KOCHTE - University of Stuttgart, Germany

• An IR-Drop Aware Test Pattern Generator for Scan-Based At-Speed Testing
  Po-Fan HOU, Yi-Tsung LIN, Jiun-Lang HUANG (National Taiwan University), Ann SHIH (Cisco Systems, Inc.), Zoe CONROY (Cisco)
• Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test
  Stephan EGGERSGLUESS (University of Bremen), Stefan HOLST (Kyushu Institute of Technology), Daniel TILLE (Infineon Technologies AG), Kohei MIYASE, Xiaoqing WEN (Kyushu Institute of Technology)
• On Optimal Power-aware Path Sensitization
  Matthias SAUER (University of Freiburg), Jie JIANG (University of Passau), Sven REIMER (University of Freiburg), Kohei MIYASE, Xiaoqing WEN (Kyushu Institute of Technology), Bernd BECKER (University of Freiburg), Ilia POLIAN (University of Passau)

Session 5A: Automatic Test Pattern Generation

Chair: Stephan EGGERSGLÜß - University of Bremen, Germany

• Automated Optimization of Scan Chain Structure for Test Compression-Based Designs
  Harshad DHOTRE (Technical University of Darmstadt), Mehdi DEHBASHI, Ulrike PFANNKUCHEN (Infineon), Klaus HOFMANN (Technical University of Darmstadt)
• Critical-Area-Aware Test Pattern Generation and Reordering
  Shingo INUYAMA, Kazuhiko IWASAKI (Tokyo Metropolitan University), Masayuki ARAI (Nihon University)
• Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation
  Harry CHEN, Simon CHEN (MediaTek Inc.), Po-Yao CHUANG, Cheng-Wen WU (National Tsing Hua University)

Session 5B: Built-In Self-Test

Chair: Hiroyuki YOTSUYANAGI - Tokushima University, Japan

• A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST
  Takaaki KATO (Kyushu Institute of Technology), Senling WANG (Ehime University), Yasuo SATO, Seiji KAJIHARA (Kyushu Institute of Technology)
• Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation
  Senling WANG, Hanan AL-AWADHI, Soh HAMADA, Yoshinobu HIGAMI, Hiroshi TAKAHASHI (Ehime University), Hiroyuki IWATA, Jun MATSUSHIMA (Renesas System Design Corp.)

Session 5C: 3D IC Testing

Chair: Jin-Fu LI - National Central University, Taiwan

• Autonomous Testing for 3D-ICs with IEEE Std. 1687
  Jin-Cun YE (National Cheng Kung University), Michael KOCHTE (University of Stuttgart), Kuen Jong LEE (National Cheng Kung Univ), Hans-Joachim WUNDERLICH (University of Stuttgart)
• Die-to-Die Clock Skew Characterization and Tuning for 3D ICs
  Shi-Yu HUANG, Chih-Chieh ZHENG (National Tsing Hua University)

25th Anniversary Panel Session: "Past, Present and Future of ATS."

 More Information

Session 6A: Special Session 4: Managing Reliability of Integrated Circuits: Lifetime Metering and Design for Healing

Organizer: Sandip KUNDU - University of Massachusetts, Amherst, USA

• Highly Dependable Multi-Processor SoCs Employing Life-Time Prediction Based on Health Monitors
  Hans KERKHOFF, Yong ZHAO (University of Twente)
• Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control
  Song BIAN, Michihiro SHINTANI (Kyoto University), Zheng WANG (Nanyang Technological University), Masayuki HIROMOTO (Kyoto University), Anupam CHATTOPADHYAY (Nanyang Technological University), Takashi SATO (Kyoto University)
• Modeling Residual Lifetime of an IC considering Spatial and Inter-Temporal Temperature Variations
  Md Nazmul ISLAM, Sandip KUNDU (University of Massachusetts Amherst)

Session 6B: Fault Tolerance

Chair: Jaan RAIK - Tallinn University of Technology, Estonia

• Functional Diagnosis for Graceful Degradation of NoC Switches
  Atefe DALIRSANI, Hans-Joachim WUNDERLICH (University of Stuttgart)
• Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology
  Aibin YAN (Anhui University), Zhengfeng HUANG, Xiangsheng FANG, Xiaolin XU, Huaguo LIANG (Heifei University of Technology)
• Quality Aware Error Detection in 2-D Separable Linear Transformation
  Shih-Hsin HU, Jacob ABRAHAM (University of Texas at Austin)

Session 6C: Analog Circuits and High-Speed I/O Test

Chair: Jiun-Lang HUANG - National Taiwan University, Taiwan

• An Optical Interconnection Test Method Applicable to 100-Gb/s Transceivers using an ATE based Hardware
  Kazuki SHIRAHATA, Takeshi MIZUSHIMA, Tasuku FUJIBE, Hidenobu MATSUMURA, Tomoyuki ITAKURA, Masahiro ISHIDA, Daisuke WATANABE (Advantest), Shin MASUDA (Advantest Laboratories)
• An Ultra-High-Speed Test Module and FPGA-based development Platform
  Te-Hui CHEN, David KEEZER (Georgia Institute of Technology)
• Parametric Fault Detection in Analog Circuits: A Statistical Approach
  Supriyo SRIMANI, Kasturi GHOSH, Hafizur RAHAMAN (IIEST, Shibpur)

Session 7A: Memory Test and Reliability

Chair: Huawei LI - Institute of Computing Technology, CAS, China

• A Test Method for Finding Boundary Currents of 1T1R Memristor Memories
  Tzu-Ying LIN, Yong-Xiao CHEN, JIN-FU LI (National Central University)
• Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories
  Shyue-Kung LU, Shang-Xiu ZHONG (National Taiwan University of Science and Technology), Masaki HASHIZUME (Tokushima University)
• Evaluation Technique for Soft-Error Rate in Terrestrial Environment Utilizing Low-Energy Neutron Irradiation
  Takumi UEZONO, Tadanobu TOBA, Kenichi SHIMBO, Fumihiko NAGASAKI, Kenji KAWAMURA (Hitachi, Ltd.)

Session 7B: Dependable Systems

Chair: Hans G. KERKHOFF - University of Twente, Netherland

• Aging-Leakage Tradeoffs Using Multi-Vth Cell Library
  Hao LUO, Mehrdad HEYDARZADEH, Mehrdad NOURANI (University of Texas at Dallas)
• Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs
  Francesco PELLEREY (Politecnico di Torino), Maksim JENIHHIN (Tallinn University of Technology), Giovanni SQUILLERO (Politecnico di Torino), Jaan RAIK (Tallinn University of Technology), Matteo SONZA REORDA (Politecnico di Torino), Valentin TIHHOMIROV, Raimund UBAR (Tallinn University of Technology)
• Combined Impact of BTI and Temperature Effect Inversion on Circuit Performance
  Warin SOOTKANEUNG (Rajamangala University of Technology Phra Nakhon), Suppachai HOWIMANPORN (King Mongkut's University of Technology North Bangkok), Sasithorn CHOOKAEW (Rajamangala University of Technology Phra Nakhon)