1. A. Yan, Y. Ling, J. Cui, Z. Chen, Z. Huang, J. Song, P. Girard, and X. Wen, "Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells based Multiple-Node-Upset-Tolerant Latch Designs," IEEE Transactions on Circuits and Systems--I: Regular Papers, Jan. 2020. (Accepted)
2. A. Yan, J. Zhou, Y. Hu, J. Cui, Z. Huang, P. Girard, and X. Wen, "Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications," IEEE Access, (Accepted)
3. T. Myint, I. Takanori, M. Amagasaki, Q. Zhao, and M. Iida, "EVALUATION OF ROUTING AREA REDUCTION FOR FINE-GRAINED OVERLAY VIRTUAL FPGA," International Journal of Innovative Computing, Information and Control, 2019.
4. K. Tashiro, M. Kurosaki, and H. Ochi, "Precoder and Postcoder Design for Wireless Video Streaming with Overloaded Multiuser MIMO-OFDM Systems," IEICE Trans. Fundamentals, vol.E102-A, no.12, pp.1825-1833, Dec. 2019.
5. A. Yan, J. Zhou, Y. Hu, J. Cui, Z. Huang, P. Girard, and X. Wen, "Novel Quadruple Cross-Coupled Memory Cell Designs with Protection against Single Event Upsets and Double-Node Upsets," IEEE Access, Vol. 7, Iss. 1, pp. 176188-176196, Dec. 2019.
6. A. Yan, Z. Xu, K. Yang, J. Cui, Z. Hunag, P. Girard, and X. Wen, "A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications," IEEE Trans. on Aerospace and Electronic Systems., DOI: 10.1109/TAES.2019.2951186, Nov. 2019. (Early Access)
7. T. Myint, M. Amagasaki, Q. Zhao, and M. Iida, "A SLM-based Overlay Architecture for FIne-grained Virtual FPGA," IEICE Electronics Express, Nov. 2019.
8. T. Ni, Y. Yao, H. Chang, L. Lu, H. Liang, A. Yan, Z. Huang, and X. Wen, "LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Oct. 2019.
9. A. Yan, X. Feng, Y. Hu, C. Lai, J. Cui, Z. Chen, K. Miyase, and X. Wen, "Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments," IEEE Trans. on Aerospace and Electronic Systems, DOI: 10.1109/TAES.2019.2925448, Jul. 2019. (Early Access)
10. A. Yan, Z. Wu, J. Guo, J. Song, and X. Wen, "Novel Double-Node-Upset-Tolerant Memory Cell Designs through Radiation-Hardening-by-Design and Layout," IEEE Trans. on Reliability, Vol. 68, No. 1, pp. 354-363, Mar. 2019.
11. A. Yan, K. Yang, Z. Huang, J. Zhang, J. Cui, X. Fang, M. Yi, and X. Wen, "A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application," IEEE Trans. on Circuits and Systems II: Express Briefs, Vol. 66, No. 2, pp. 287-291, Feb. 2019.
12. Yan, C. Lai, Y. Zhang, C. Liu, Z. Chen, Q. He, Z. Huang, and X. Wen, "Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS," IEEE Trans. on Emerging Topics in Computing, DOI: 10.1109/TETC.2018.2871861, Sep. 2018. (Early Access)
13. T. Ariyoshi, J. Iwasa, Y. Takane, K. Sakamoto, A. Baba, and Y. Arima, ”Modulation transfer function analysis of silicon X-ray sensor with trench-structured photodiodes”, IEICE Electronics Express, Vol.15, No.11, pp.20180177-1 - 20180177-6, Jun. 2018
14. I. Syafalni, T. Sasao, and X. Wen, "A Method to Detect Bit Flips in a Soft-Error Resilient TCAM," IEEE Trans. on Computer-Aided Design, Vol. 37, No. 6, pp. 1185-1196, Jun. 2018.
15. T. Ariyoshi, Y. Takane, J. Iwasa, K. Sakamoto, A. Baba, and Y. Arima，”Silicon trench photodiodes on a wafer for efficient X-ray-to-current signal conversion using side-X-ray-irradiation mode”, Japanese Journal of Applied Physics, Vol.57, No.4S, pp.04FH04-1-04FH04-6, Mar. 2018.
16. D. Nishikata, M.A.B.M. Ali, K. Hosoda, H. Matsumoto, K. Nakamura, "Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator", Japanese Journal of Applied Physics, Vol.57, No.4S, pp.04FF11-1-5, Mar. 19, 2018.
17. Q. Zhao, M. Amagasaki, M. Iida, M. Kuga, and T. Sueyoshi, "Enabling FPGA-as-a-Service in the Cloud with hCODE Platform," IEICE Transactions on Information and Systems, Vol.E101.D, No.2, pp.335-343, Feb. 2018.
18. M. Amagasaki, M. Ikebe, Q. Zhao, M. Iida, and T. Sueyoshi, "Three Dimensional FPGA Architecture with Fewer TSVs," IEICE Transactions on Information and Systems, Vol.E101.D, No.2, pp.278-287, Feb. 2018.
19. T. T. T. Nguyen, L. Lanante, S. Yoshizawa, and H. Ochi, "Low Latency IDMA with Interleaved Domain Architecture for 5G Communications," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol.7, issue 4, pp.582-593, Dec. 2017.
20. T. Kato, S. Wang, Y. Sato, S. Kajihara, and X. Wen, "A Flexible Scan-In Power Control Method in Logic BIST and Its Evaluation with TEG Chips," IEEE Trans. on Emerging Topics in Computing, Oct. 2017. (Early Access)
21. K. Tashiro, L. Lanante, M. Kurosaki, and H. Ochi, "Joint transmission and coding scheme for high-resolution video streams over multiuser MIMO-OFDM systems," IEICE Trans. Fundamentals, vol.E100-A, no.11, pp.2304-2313, Nov. 2017.
22. Q. Zhao, M. Amagasaki, M. Iida, M. Kuga, and T. Sueyoshi, "Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost," IPSJ Trans. on System LSI Design Methodology, Vol.10, pp.63-70, Aug. 2017.
23. 上井竜己, 長尾勇平, ラナンテレオナルドジュニア, 黒埼正行, 尾知博, "OFDMAランダムアクセスのマルコフ連鎖モデル化とその性能解析," 電子情報通信学会論文誌（B）, vol.J100-B, no.7, pp.492-504, July 2017.
24. A. Xiang, X. Wen, and L.-T. Wang, "Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudo-Random Test Pattern Generation and Reseeding," IEEE Trans. on VLSI Systems, Vol. 25, No. 3, pp. 942-953, Mar. 2017.
25. T. Ariyoshi, S. Funaki, K. Sakamoto, A. Baba, and Y. Arima, “X-ray-to-current signal conversion characteristics of trench-structured photodiodes for direct-conversion-type silicon X-ray sensor”, Japanese Journal of Applied Physics, 56巻 4S号 （頁 04CH06-1 〜 04CH06-5）, Feb. 2017.
26. F. Li, X. Wen, K. Miyase, S. Holst, and S. Kajihara, "Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation," IEICE Trans. on Fundamentals of Electronics, Communications, and Computer Sciences, Vol. E99-A, No. 12, pp. 2310-2319, Dec. 2016.
27. T.T.T. Nguyen, L. Lanante, Y. Nagao, and H. Ochi, “Multi-User MIMO Channel Emulator with Automatic Channel Sounding Feedback,” IEICE Transactions on Fundamentals, vol. E99-A, no. 11, pp.1918-1927, Nov. 2016.
28. Y. Miyake, Y. Sato, S. Kajihara, and Y. Miura, "Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor," IEEE Trans. on Very Large Scale Integration Systems, Volume: 24, No. 11, pp.3282-3295, Nov. 2016.
29. T. Chen, D. Shen, X. Yi, H. Liang, X. Wen, and W. Wang, "Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures," IEICE Trans. on Inf. & Syst., Vol. E99-D, No. 11, pp. 2672-2681, Nov. 2016.
30. N. Sutisna, R. Hongyo, L. Lanante Jr., Y. Nagao, M. Kurosaki, H. Ochi, "Unified HW/SW Co-Verification Methodology for High Throughput Wireless Communication System", IPSJ Transaction on System LSI Design Methodology, Vol.9, pp.61-71, Aug. 2016.
31. Y. Kohara, N. Kubo, T. Nishiyama, T. Koizuka, M. Alimudin, A. Rahmat, H. Okamura, T. Yamanokuchi, K. Nakamura, "Self-stabilization techniques for intermediate power level in stacked-Vdd integrated circuits using DC-balanced coding methods", Japanese Journal of Applied Physics, Vol.55, No.4S, pp.04EF06-1-7, Apr. 2016.
他：国際会議論文 97件、国内会議 50件以上