| Abstract |
Abstract:
Scaling of CMOS integrated circuits is becoming difficult due to
increase in power dissipation and device variations. Two future
directions in IC technology are in prospect; "More Moore" by the
conventional device scaling and "More than Moore" by
System-in-Package (SiP). This talk will present some of the
recent research achievements on 3D system integration by
SiP. Especially focus will be placed on CMOS proximity
inter-chip communications. Capacitive and inductive coupling
I/Os are emerging non-contact parallel links for chips that are
stacked in a package. They are implemented by digital circuits
in a standard CMOS. No new wafer process or mechanical process
is required, and hence inexpensive. Since there is no pad
exposed for contact, ESD protection structure can be
removed. Chips under difference supply voltages can be directly
connected, because they provide with an AC-coupling
interface. In the talk, fundamental differences between the
inductive coupling and the capacitive coupling will be
discussed. Advantages of the inductive coupling over
Through-Silicon-Vias and micro-bumps will then be referred
to. Circuit techniques to raise aggregated data rate to 1Tb/s,
perform burst data transmission at 11Gb/s/channel, lower energy
dissipation to 0.1pJ/b, and extend communication ranges over 1mm
will be presented. Lastly, future challenges and opportunities
such as a 3D scaling scenario will be described.
Presenter biography:
Tadahiro Kuroda received the Ph.D. degree in electrical engineering
from the University of Tokyo, Tokyo, Japan, in 1999. In 1982, he
joined Toshiba Corporation, where he designed CMOS SRAMs, gate
arrays and standard cells. From 1988 to 1990, he was a Visiting
Scholar with the University of California, Berkeley, where he
conducted research in the field of VLSI CAD. In 1990, he was
back to Toshiba, and engaged in the research and development of
BiCMOS ASICs, ECL gate arrays, high-speed CMOS LSIs for
telecommunications, and low-power CMOS LSIs for multimedia and
mobile applications. He invented a Variable Threshold-voltage
CMOS (VTCMOS) technology to control VTH through substrate bias,
and applied it to a DCT core processor and a gate-array in
1995. He also developed a Variable Supply-voltage scheme using
an embedded DC-DC converter, and employed it to a microprocessor
core and an MPEG-4 chip for the first time in the world in
1997. In 2000, he moved to Keio University, Yokohama, Japan,
where he has been a professor since 2002. He was a Visiting
Professor at Hiroshima University, Japan, and is a Visiting
MacKay Professor at the University of California, Berkeley. His
research interests include ubiquitous electronics, sensor
networks, wireless and wireline communications, and
ultra-low-power CMOS circuits. He has published more than 200
technical publications, including 50 invited papers, and 18
books/chapters, and has filed more than 100 patents. Dr. Kuroda
served as the General Chairman for the Symposium on VLSI
Circuits, the Vice Chairman for ASP-DAC, sub-committee chairs
for A-SSCC, ICCAD, and SSDM, and program committee members for
the Symposium on VLSI Circuits, CICC, DAC, ASP-DAC, ISLPED,
SSDM, ISQED, and other international conferences. He is a
recipient of the 2005 IEEE System LSI Award, the 2005 P&I Patent
of the Year Award, the 2006 LSI IP Design Award, the 2006 IP/SoC
Best Design Paper Award, and the 2007 ASP-DAC Best Design
Award. He is an IEEE Fellow, an elected AdCom member for the
IEEE Solid-State Circuits Society and an IEEE SSCS Distinguished
Lecturer.
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