| 内容梗概 |
1. An Optimization Framework for Embedded Processors with
Auto-Addressing Mode
Modern embedded processors with dedicated address generation
unit support memory accesses through auto-increment/decrement
addressing mode. The auto-increment/decrement mode, if properly
utilized, can save address arithmetic instructions, reduce
static and dynamic memory footprint of the program and speed up
the execution as well.
[Liao 1995; 1996] categorized this problem as simple offset
assignment (SOA) and general offset assignment (GOA), which
involves storage layout of variables and assignment of address
registers respectively proposing several heuristic
solutions. Two important directions of work have been followed
subsequently for solving the SOA problem: the first one involves
coming up with better heuristics for graph algorithms for offset
assignment and second one involves improving the performance of
Liao's solution by undertaking program reordering which
rearranges the code sequence.
This work proposes a *new direction* for investigating the
solution space of the problem. The general idea is to perform
simplification of the underlying access graph through
coalescence of the memory locations of program variables. A
comprehensive framework is proposed including coalescence-based
offset assignment and post-pre optimization. Variables not
interfering with other (not simultaneously live at any program
point) can be coalesced into the same memory
location. Coalescing allows simplifications of the access graph
yielding better SOA solutions; it also reduces the address
register pressure to such low values that some GOA solutions
become optimal. Moreover, it can reduce the memory footprint
both statically and at runtime for stack variables. Besides,
variable coalescence is orthogonal to other heuristics earlier
proposed and thus can be integrated with the other approaches. A
key limitation to the use of auto-addressing modes by production
compilers is the limited scope of its applicability. Typically,
this optimization has been performed only within basic blocks
which severely limits its utility. Our second optimization
(post/pre optimization) considers both post- and pre-
modification mode for optimizing code across basic blocks which
makes it useful. Making use of both addressing modes further
reduces SOA/GOA cost and our post-pre optimization phase is
optimal in selecting post or pre mode after variable offsets
have been determined.
We have shown the advantages of our framework over previous
approaches to capture more opportunities to reduce both stack
size and SOA/GOA cost leading to more speedup. The algorithms
are evaluated on a commercial compiler provided by Motorola to
boost code generation performance on the DSP 56000 chip. Our
results show that the cost can be reduced by 70~80% for
Single-AR and Multiple-AR, almost doubling the cost reduction
from a baseline solver. On the other hand, coalescence-based
approach can also shrink the stack size a lot. We observe a
significant reduction of 63~74% for Single-AR and
Multiple-AR. Furthermore, the optimization phases after
coalescence-based offset assignment including program reordering
and post/pre optimization contribute to more cost reduction as
well. The overall cycle reduction is up to 8.28%.
2. Challenges and Approaches in Providing Quality of Service in Chip
Multi-Processor Systems
In this talk, I will discuss problems related to the impact of
sharing fine-grain platform resources among cores, for example
the lowest level cache. We will show how different applications
are affected by cache sharing. In particular, we will highlight
the types and severity of pathological performance cases that
can arise when applications run together on different cores but
sharing the lowest level cache.
The trends in enterprise IT toward service-oriented computing,
server consolidation, and virtual computing point to a future in
which workloads are becoming increasingly diverse in terms of
performance, reliability, and availability requirements. In
this environment, it is desirable to have microarchitecture and
software support that can provide a guarantee of a certain level
of performance (Quality of Service or QoS). We will present a
framework for multicore architectures to fully provide QoS. We
found that in addition to the ability to partition platform
resources, a full QoS framework also needs an appropriate way to
specify a QoS target, and an admission control policy that
accepts jobs only when their QoS targets can be satisfied. We
also found that providing strict QoS often leads to a
significant reduction in throughput due to resource
fragmentation. We will show throughput optimization techniques
that include: (1) exploiting various QoS execution modes, and
(2) a microarchitecture technique that steals excess resources
from a job while still meeting its QoS target.
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