IEEE Circuits and Systems
Society
Fukuoka Chapter
Officers 2009
| Chair Person: | Tsutomu Sasao | Kyushu Institute of Technology E-mail: sasao at cse dot kyutech dot ac dot jp |
| Vice Chair Person: | Vasily Moshnyaga | Fukuoka University E-mail: vasily at fukuoka minus u dot ac dot jp |
| Secretary/Treasurer: | Toshinori Sato | Fukuoka University E-mail: casfukuoka at fukuoka minus u dot ac dot jp |
Last Update: June 19, 2009
2009 Activity Plans
Activity Reports
June 18, Technical Meeting
| Title | Studies on Evaluating Cache Memory Architectures |
| Presenter | Dr. Takatsugu Ono (Kyushu University) |
 Dr. Ono |
|
| Place |
Fukuoka University,
Dept. Electronics Engineers and Computer Science Computer Systems Laboratory Room#1 8-19-1 Nanakuma, Jonan-ku, Fukuoka |
| DATE | June 18, 2009 (Thu.) 16:30 - 17:30 |
| Attendees | 14 (including 3 IEEE members) |
| Abstract | Dr. Ono will present his latest studies on evaluation techniques for cache memory architectures. |
| Registration |
Toshinori Sato (casfukuoka @ fukuoka-u.ac.jp) Due date: June 14 (Sun.) |
May 23, Technical Meeting
| Title | History of Research on Switching Theory in Japan - On the Contributions of Akira Nakashima |
| Presenter | Akihiko Yamada (Computer Systems Lab.) |
 Prof. Yamada |
|
| Place |
Naha Calture Center TENBUSU English information at RM-2009 web page |
| DATE | May 23, 2009 (Sat) 19:40 - 20:05 |
| Attendees | 27 (including 15 IEEE members) |
| Abstract | This talk introduces the history of switching theory in Japan, mainly on the contributions of Akira Nakashima. Also, it compares the work of Nakashima with that of Shannon. |
| Co-located workshop | Reed-Muller Workshop (RM-2009) |
May 23, Technical Meeting
| Title | Designing and Using FPGAs Beyond Classical Binary Logic: Opportunities in Nano-scale Integration Age |
| Presenter |
Zeljko Zilic (McGill University, Canada) |
| Place |
Okinawa Industory Support Center English information (PDF) at ISMVL-2009 web page |
| DATE | Canceled |
| Abstract | Field Programmable Gate Arrays (FPGAs) have been a great prototyping and implementation technology for two decades. In this paper, we first recap the rationale beyond the (non)-acceptance of multi-valued logic in implementing FPGAs so far, explaining the most critical technological and tool support details. Then, we outline the critical applications of FPGAs (e.g., emulation) where the non-binary nature can be exploited by MVL implementation. Finally, we highlight the most significant opportunities that present themselves with the transition to the nano-scale system implementations. |
| Co-located symposium | 39th International Symposium on Multiple-Valued Logic (ISMVL-2009) |
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Links
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IEEE | |
| IEEE Japan Council | ||
| IEEE Fukuoka Section | ||
