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Design for Test

  1. T. Ni, Q. Xu, Z. Huang, A. Yan, and X. Wen, "A Cost-Effective TSV Repair Architecture for Clustered Faults in 3D IC", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, DOI: 10.1109/TCAD.2020.3025169, 2020. (Early Access )
  2. T. Ni, Y. Yao, H. Chang, X. Zhang, L. Lu, A. Yan, Z. Huang, and X. Wen, "A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology", IEEE Trans. on Emerging Topics in Computing, SI: Emerging Trends and Computing Paradigms for Testing, Reliability and Security in Future VLSI Systems, DOI: 10.1109/TETC.2020.2969237, 2020. (Early Access)
  3. T. Ni, H. Chang, T. Song, Q. Xu, Z. Huang, H. Liang, A. Yan, and X. Wen, "Non-intrusive Online Distributed Pulse Shrinking Based Interconnect Testing in 2.5D IC", IEEE Trans. on Circuits and Systems II: Express Briefs, Vol. 67, No. 11, pp. 2657-2661, Nov. 2020.
  4. T. Ni, Y. Yao, H. Chang, L. Lu, H. Liang, A. Yan, Z. Huang, and X. Wen, "LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 39, Iss. 10, pp. 2938-2951, Oct. 2020.
  5. T. Ni, M. Nie, H. Liang, J. Bian, X. Xu, X. Fang, Z. Huang, and X. Wen, "Vernier Ring Based Pre-bond Through Silicon Vias Test in 3D ICs", IEICE Electronics Express, Vol. 18, No. 14, Letter 20170590, Oct. 2017.
  6. L.-T. Wang, N. A. Touba, M. S. Hsiao, J.-L. Huang, C.-M. Li, S. Wu, X. Wen, M. Bhattarai, F. Li, and Z. Jiang, "Architectures for Testing 3D Chips Using Time-Division Demultiplexing/Multiplexing", Proc. of IEEE Int'l Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Paper 5.4, Anaheim, USA, Sep. 2011.
  7. S. Wu, L.-T. Wang, X. Wen, Z. Jiang, M. Hsiao, W.-B. Jone, L. Tan, Y. Zhang, Y. Hu, C.-M. Li, J.-L. Huang, and L. Yu, "Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, No. 3, pp. 455-463, Mar. 2011.
  8. L.-T. Wang, R. Apte, S. Wu, B. Sheu, K.-J. Lee, X. Wen, W.-B. Jone, C.-H. Yeh, J. Guo, J. Liu, and Y.-C. Sung, "Turbo1500: Core-Based Design for Test and Diagnosis Using IEEE Std. 1500", IEEE Design & Test of Computers, Vol. 26, No. 1, pp. 26-35, Jan. 2009.
  9. L.-T. Wang, R. Apte, S. Wu, B. Sheu, K.-J. Lee, X. Wen, W.-B. Jone, C.-H. Yeh, W.-S. Wang, H.-J. Chao, J. Guo, J. Liu, Y. Niu, Y.-C. Sung, C.-C. Wang, and F. Li, "Turbo1500: Toward Core-Based Design for Test and Diagnosis Using IEEE Std. 1500", Proc. of IEEE Int'l Test Conf., Paper 29.3, Santa Clara, USA, Oct. 2008.
  10. H. Furukawa, X. Wen, L.-T. Wang, B. Sheu, Z. Jiang, and S. Wu, "A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing", Proc. of IEEE Int'l Test Conf., Paper 17.2, Santa Clara, USA, Oct. 2006.
  11. X. Wen, K. K Saluja, and K. Kinoshita, "Testing Core-Based System-on-a-Chip Designs", 信頼性学会誌, Vol. 23, No. 4, pp. 371-383, May 2001.
  12. H. Yokoyama, X. Wen, and H. Tamamoto, "Random Pattern Testable Design with Partial Circuit Duplication", Proc. of IEEE Asian Test Symp., pp. 353-358, Akita, Japan, Nov. 1997.
  13. K. K. Saluja, R. Chou, X. Wen, and L. Nachman, "Synthesis, Testing and Diagnosis of Faults in Digital Circuits", Computer-Aided Design, Test, and Evaluation for Dependability, International Academic Publishers, pp. 236-245, Jun. 1996.
  14. X. Wen, H. Tamamoto, and K. Kinoshita, "Testing of k-FR Circuits under Highly Observable Condition", IEICE Trans. on Inf. & Syst., Vol. E78-D, No. 7, pp. 830-838, Jul. 1995.
  15. X. Wen, H. Tamamoto, and K. Kinoshita, "A New Testable Design of Logic Circuits under Highly Observable Condition", Proc. of IEEE Asian Test Symp., pp. 195-200, Nara, Japan, Nov. 1994.
  16. X. Wen and K. Kinoshita, "Testable Designs of Sequential Circuits under Highly Observable Condition", Proc. of IEEE Int’l Test Conf., pp. 632-641, Baltimore, USA, Sep. 1992.
  17. X. Wen and K. Kinoshita, "A Testable Design of Sequential Circuits under Highly Observable Condition", IEICE Trans. on Inf. & Syst., Vol. E75-D, No. 3, pp. 334-341, May 1992.
  18. X. Wen and K. Kinoshita, "A Testable Design of Logic Circuits under Highly Observable Condition", IEEE Trans. on Computers, Vol. 41, No. 5, pp. 654-659, May 1992.
  19. X. Wen and K. Kinoshita, "A Testable Design of Logic Circuits under Highly Observable Condition", Proc. of IEEE Int’l Test Conf., pp. 955-963, Washington DC, USA, Sep. 1990.
  20. X. Wen and K. Kinoshita, "Fault Detection and Diagnosis of k-UCP Circuits under Totally Observable Condition", Proc. of IEEE Int’l Symp. on Fault-Tolerant Computing, pp. 382-389, Newcastle Upon Tyne, UK, Jun. 1990.
  21. 樹下行三，温暁青，スダーカ Ｍ．レディ, "全可観測な環境でのNAND 論理回路のスタックオープン故障の検査手法について", 電子情報通信学会論文誌 D-I, Vol. J73-D-I, No. 2, pp. 245-252, 1990年2月.
  22. K. Kinoshita, X. Wen, and S. M. Reddy, "Diagnostic Testing of NAND Logic Circuits under Totally Observable Condition", Proc. of Joint Symp. on Fault-Tolerant Computing, pp. 69-74, Chongqing, China, Jul. 1989.