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Fault Diagnosis

  1. S. Holst, M. Kampmann, A. Sprenger, J. D. Reimer, S. Hellebrand, H.-J. Wunderlich, and X. Wen, "Logic Fault Diagnosis of Hidden Delay Defects," Proc. of Int'l Test Conf., Paper 5B.2, Washington, D.C., USA, Nov. 2020.
  2. S. Holst, E. Schneider, M. A. Kochte, X. Wen, and H.-J. Wunderlich, "Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data," Proc. of Int'l Test Conf., Paper 3.1, Washington, D.C., USA, Nov. 2019.
  3. S. Holst, E. Schneider, M. A. Kochte, X. Wen, and H.-J. Wunderlich, "Small Delay Fault Diagnosis with Compacted Responses," Poster at ACM Design Automation Conf., Las Vegas, USA, Jun. 2019.
  4. Y. Yamato, Y. Nakamura, K. Miyase, X. Wen, and S. Kajihara, "A Novel Per-Test Fault Diagnosis Method Based On the Extended X-Fault Model for Deep-Submicron LSI Circuits," IEICE Trans. on Inf. & Syst., Vol. E91-D, No. 3, pp. 667-674, Mar. 2008.
  5. I. Polian, Y. Nakamura, P. Engelke, S. Spinner, K. Miyase, S. Kajihara, B. Becker, and X. Wen, "Diagnosis of Realistic Defects Based on X-Fault Model," Proc. of IEEE Intl. Workshop on Design and Diagnostics of Electronic Circuits and Systems, 263-266, Bratislava, Slovakia, Apr. 2008.
  6. X. Wen, S. Kajihara, K. Miyase, Y. Yamato, L.-T. Wang, K. K. Saluja, and K. Kinoshita, "A Per-Test Fault Diagnosis Method Based on the X-Fault Model," IEICE Trans. on Inf. & Syst., Vol. E89-D, No. 11, pp. 2756-2765, Nov. 2006.
  7. X. Wen, Y. Yamato, K. Miyase, S. Kajihara, H. Furukawa, L.-T. Wang, K. K. Saluja, and K. Kinoshita, "An Improved Method of Per-Test X-Fault Diagnosis for Deep-Submicron LSI Circuits," Proc. of IEEE Workshop on RTL and High Level Testing, pp. 55-60, Fukuoka, Japan, Nov. 2006. (Best Paper Award)
  8. N. Toyota, X. Wen, S. Kajihara, and M. Sanada, "On Quantifying Observability for Fault Diagnosis of VLSI Circuits," Proc. of IEEE Workshop on RTL and High Level Testing, pp. 192-197, Harbin, China, Jul. 2005.
  9. X. Wen, H. Tamamoto, K. K. Saluja, and K. Kinoshita, "Fault Diagnosis for Physical Defects using Unknown Behavior Model," Journal of Computer Science and Technology, Vol. 20, No. 2, pp. 187-194, Mar. 2005.
  10. X. Wen, T. Miyoshi, S. Kajiihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita, "On Per-Test Fault Diagnosis Using the X-Fault Model," Proc. of IEEE/ACM Int'l Conf. on Computer Aided Design, pp. 633-640, San Jose, USA, Nov. 2004.
  11. X. Wen, H. Tamamoto, K. K. Saluja, and K. Kinoshita, "Fault Diagnosis for Physical Defects of Unknown Behaviors," Proc. of IEEE Asian Test Symp., pp. 236-241, Xi'An, China, Nov. 2003.
  12. X. Wen, T. Honzawa, H. Tamamoto, K. K. Saluja, and K. Kinoshita, "Design for Diagnosability for CMOS Circuits," Proc. of IEEE Asian Test Symp., pp. 144-149, Singapore, Dec. 1998.
  13. X. Wen, H. Tamamoto, K. K. Saluja, and K. Kinoshita, "Transistor Leakage Fault Diagnosis for CMOS Circuits," IEICE Trans. on Inf. & Syst., Vol. E81-D, No. 7, pp. 697-705, Jul. 1998.
  14. X. Wen, H. Tamamoto, K. K. Saluja, and K. Kinoshita, "Transistor Leakage Fault Diagnosis using IDDQ and Logic Information," IEICE Trans. on Inf. & Syst., Vol. E81-D, No. 4, pp. 372-381, Apr., 1998.
  15. X. Wen, H. Tamamoto, K. K. Saluja, and K. Kinoshita, "Fault Diagnosis for Static CMOS Circuits," Proc. of IEEE Asian Test Symp., pp. 282-287, Akita, Japan, Nov. 1997.
  16. X. Wen, K. K. Saluja, K. Kinoshita, and H. Tamamoto, "Transistor Leakage Fault Location for Static CMOS Circuits," Computer-Aided Design, Test, and Evaluation for Dependability (International Academic Publishers), pp. 297-302, Jun. 1996.
  17. X. Wen, K. Kinoshita, H. Tamamoto, and H. Yokoyama, "Efficient Guided-Probe Fault Location Method for Sequential Circuits," IEICE Trans. on Inf. & Syst., Vol. E78-D, No. 2, pp. 122-129, Feb. 1995.
  18. X. Wen, N. Itazaki, and K. Kinoshita, "Efficient Methods for Guided-Probe Diagnosis," IEICE Trans. on Inf. & Syst., Vol. E76-D, No. 7, pp. 817-825, Jul. 1993.