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Reliability

  1. A. Yan, Z. Fan, Z. Xu, J. Cui, X. Chen, Z. Huang, T. Ni, H. Bao, and X. Wen, "QRHIL: A QNU-Recoverable and HIS-Insensitive Latch Design for Space Applications in Harsh Radiation Environments," WIP Presentation at IEEE/ACM Design Automation Conf., San Francisco, USA, Dec. 2021. (Accepted)
  2. A. Yan, L. Ding, C. Shan, H. Cai, X. Chen, Z. Wei, Z. Huang, and X. Wen, "TPDICE and SIM based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation," IEEE Int'l Symp. on Circuits and Systems, pp. ???-???, Daegu, Korea, May 2021. (Accepted)
  3. Q. Xu, J. Wang, H. Geng, S. Chen, and X. Wen, "Reliabikity-Driven Neuromorphic Computing Systems Design," Proc. of Design, Automation and Test in Europe, Paper 11.7.2, Grenoble, France, Feb. 2021.
  4. A. Yan, C. Lai, Y. Zhang, C. Liu, Z. Chen, Q. He, Z. Huang, and X. Wen, "Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS," IEEE Trans. on Emerging Topics in Computing, Vol. 9, No. 1, pp. 520-533, Jan.-Mar. 2021.
  5. A. Yan, Y. Chen, Y. Hu, J. Zhou, T. Ni, J. Cui, P. Girard, and X. Wen, "Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets," IEEE Trans. on Circuits and Systems I: Regular Papers, Vol. 67, No. 12, pp. 4684-4695, Dec. 2020.
  6. A. Yan, Y. Chen, J. Zhou, J. Cui, T. Ni, X. Wen, and P. Girard, "A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets," Proc. of IEEE Asian Test Symp., Paper A2-1, Penang, Malaysia, Nov. 2020.
  7. R. Ma, S. Holst, X Wen, A. Yan, and H. Xu, "A Novel High Performance Scan-Test-Aware Hardened Latch Design," Proc. of IEEE Workshop on RTL and High Level Testing, Paper 2.2, Penang, Malaysia, Nov. 2020.
  8. A. Yan, Z. Xu, Y. Ling, Ji.Cui, Z. Ying, P. Girard, and X. Wen, "Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications," Proc. of IEEE Int'l Symp. on Circuits & Systems, pp. 1-5, Seville, Spain, Oct. 2020.
  9. A. Yan, Y. Chen, Z. Xu, Z. Chen, J. Cui, Z. Huang, P. Girard, X. Wen, "Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low Power and Low-Orbit Aerospace Applications," IEEE Trans. on Aerospace and Electronic Systems, Vol. 56, No. 5, pp. 3931-3940, Oct. 2020.
  10. Y. Yan, Z. Xu, X. Feng, J. Cui, Z. Chen, T. Ni, Z. Huang, P. Girard, and X. Wen, "Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation Environments," IEEE Transactions on Emerging Topics in Computing, DOI: 10.1109/TETC.2020.3025584, Sep. 2020. (Early Access)
  11. A. Yan, J. Zhou, Y. Hu, Y. Chen, T. Ni, J. Cui, P. Girard, and X. Wen, "Dual Interlocked Storage Cells Based Double Node Upset Self Recoverable Flip Flop Design for Safety Critical Applications," Proc. of IEEE Int'l Test Conf. in Asia, Paper C2-1, Taipei, Taiwan, Sep. 2020.
  12. A. Yan, J. Zhou, Y. Hu, J. Cui, Z. Huang, P. Girard, and X. Wen, "Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications," IEEE Access. (Accepted)
  13. Z. Dou, A. Yan, J. Zhou, Y. Hu, Y. Chen, T. Ni, J. Cui, P. Girard, and X. Wen, "Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors," Proc. of IEEE Int'l Test Conf. in Asia, pp. 35-40, Taipei, Taiwan, Sep. 2020.
  14. A. Yan, Z. Xu, K. Yang, J. Cui, Z. Hunag, P. Girard, and X. Wen, "A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications," IEEE Trans. on Aerospace and Electronic Systems, Vol. 56, No. 4, pp. 2666-2676, Aug. 2020.
  15. A. Yan, X. Feng, X. Zhao, H. Zhou, J. Cui, Z. Ying, P. Girard, and X. Wen, "HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filtering Latch for Safety-Critical Applications," Proc. of IEEE/ACM Design Automation Conf., Paper 63.2, San Francisco, USA, Jul. 2020.
  16. A. Yan, Y. Chen, X. Feng, Z. Chen, Z. Ying, T. Ni, P. Girard, and X. Wen, "N-1 Errors Interceptive Multiple-Modular-Redundancy Voter Designs for Safety-Critical Applications," Poster at IEEE/ACM Design Automation Conf., San Francisco, USA, Jul. 2020.
  17. A. Yan, Y. Hu, J. Cui, Z. Chen, Z. Huang, T. Ni, P. Girard, and X. Wen, "Information Assurance through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment," IEEE Trans. on Computers, Vol. 69, No. 6, pp. 789-799, Jun. 2020.
  18. A. Yan, X. Feng, Y. Hu, C. Lai, J. Cui, Z. Chen, K. Miyase, and X. Wen, "Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments," IEEE Trans. on Aerospace and Electronic Systems, Vol. 52, No. 2, pp. 1163-1171, Apr. 2020.
  19. A. Yan, Y. Ling, J. Cui, Z. Chen, Z. Huang, J. Song, P. Girard, and X. Wen, "Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells based Multiple-Node-Upset-Tolerant Latch Designs," IEEE Trans. on Circuits and Systems--I: Regular Papers, Vol. 67, No. 3, pp. 879-890, Mar. 2020.
  20. A. Yan, J. Zhou, Y. Hu, J. Cui, Z. Huang, P. Girard, and X. Wen, "Novel Quadruple Cross-Coupled Memory Cell Designs with Protection against Single Event Upsets and Double-Node Upsets," IEEE Access, Vol. 7, No. 1, pp. 176188-176196, Dec. 2019.
  21. A. Yan, Z. Wu, L. Lu, Z. Chen, J. Song, Z. Ying, P. Girard, and X. Wen, "Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications," Proc. of IEEE Asian Test Symp., pp. 43-48, Kolkata, India, Dec. 2019.
  22. A. Yan, Z. Wu, J. Zhou, Y. Hu, Y. Chen, Z. Ying, X. Wen, and P. Girard, "Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications," Proc. of IEEE Asian Test Symp., pp. 55-60, Kolkata, India, Dec. 2019.
  23. A. Yan, Z. Wu, J. Zhou, Y. Hu, Y. Chen, and X. Wen, "Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications," Poster at IEEE Int'l Conf. on Computer Design, Abu Dhabi, United Arab Emirates, Nov. 2019.
  24. C. M. Fuchs, P. Choux, X. Wen, N. M. Murilloy, G. Furanoz, S. Holst, A. Tavoularisz, S.-K. Lu, and A. Plaat, "A Fault-Tolerant MPSoC for CubeSats," Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Paper S4-2, Delft, Netherlands, Oct. 2019.
  25. Z. Song, A. Yan, J. Cui, Z. Chen, X. Li and X. Wen, "A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells," Proc. of IEEE Int'l Test Conf. in Asia, pp. 139-144, Tokyo, Japan, Sep. 2019.
  26. R. Ma, S. Holst, X. Wen, A. Yan, and H. Xu, "STAHL: A Novel Scan-Test-Aware Hardened Latch Design," Proc. of IEEE European Test Symp., Paper 4B-2, Baden Baden, Germany, May 2019.
  27. A. Yan, Y. Hu, J. Song, and X. Wen, "Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications," Proc. of Design, Automation and Test in Europe, pp. 1658-1663, Florence, Italy, Mar. 2019.
  28. A. Yan, Z. Wu, J. Guo, J. Song, and X. Wen, "Novel Double-Node-Upset-Tolerant Memory Cell Designs through Radiation-Hardening-by-Design and Layout," IEEE Trans. on Reliability, Vol. 68, No. 1, pp. 354-363, Mar. 2019.
  29. A. Yan, K. Yang, Z. Huang, J. Zhang, J. Cui, X. Fang, M. Yi, and X. Wen, "A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application," IEEE Trans. on Circuits and Systems II: Express Briefs, Vol. 66, No. 2, pp. 287-291, Feb. 2019.
  30. A. Yan, Y. Ling, J. Cui, Z. Chen, J. Song, and X. Wen, "Novel Multiple-Node-Upset-Tolerant Latch Designs through Radiation-Hardening-by-Design Technique for Nanoscale CMOS Technology," Proc. of China Test Conf., Harbin, China, Aug. 2018. (Best Paper Award)
  31. I. Syafalni, T. Sasao, and X. Wen, "Bit-Flip Errors Detection Using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM," Proc. of Int'l Workshop on Logic and Synthesis, pp. 124-131, San Francisco, USA, Jun. 2018.
  32. I. Syafalni, T. Sasao, and X. Wen, "A Method to Detect Bit Flips in a Soft-Error Resilient TCAM," IEEE Trans. on Computer-Aided Design, Vol. 37, No. 6, pp. 1185-1196, Jun. 2018.
  33. S. Holst, R. Ma, and X. Wen, "The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches," Proc. of IEEE European Test Symp., Paper 7A-1, Bremen, Germany, May-Jun. 2018.
  34. I. Syafalni, T. Sasao, and X. Wen, "Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM," Proc. of IEEE Computer Society Annual Symp. on VLSI, pp. 679-684, Pittsburgh, USA, Jul. 2016.
  35. I. Syafalni, T. Sasao, and X. Wen, "A Soft-Error Tolerant TCAM for Multiple-Bit Flips Using Partial Don't Care Keys," Proc. of Int'l Workshop on Logic and Synthesis, pp. 11-18, Mountain View, USA, Jun. 2015.
  36. I. Syafalni, T. Sasao, X. Wen, S. Holst, and K. Miyase, "A Soft-Error Tolerant TCAM Using Partial Don’t-Care Keys," Poster at IEEE European Test Symp., Cluj-Napoca, Romania, May 2015.
  37. I. Syafalni, T. Sasao, X. Wen, and S. Holst, "Techniques for Mitigating Soft Errors in TCAMs," Proc. of Int'l Symp. on Dependable Integarted Systems, Fukuoka, Japan, Mar. 2015.
  38. I. Syafalni, T. Sasao, X. Wen, S. Holst, and K. Miyase, "Soft-Error Tolerant TCAMs for High-Reliability Packet Classification," Proc. of IEEE Asia Pacific Conf. on Circuits and Systems, pp. 471-474, Ishigaki Island, Japan, Nov. 2014.