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• 2017.4-2021.3: Japan Society for the Promotions of Science Grant-in-Aid for Scientific Research (B) 17H01716 / Shift-Power-Safe Scan Test Methodology for High-Quality Low-Power Circuits

• 2016.4-2022.3: MEXT & Kyushu Institute of Technology Grant for Function Enhancement / Establishing International Research and Education Center for Highly-Reliable LSI Technology in the Safe-and-Secure Super-Smart Society

• 2016.6-2021.3: Kyushu Institute of Technology Grant for University Reform Projects / Practical Education Program for LSI Professionals

• 2020.1-2023.12: National Natural Science Foundation of China #61974001 / Research on Design for Hardened Storage Cells against Single-Event Multiple-Node-Upset and Multiple-Transient

• 2017.9-2019.3: Kyushu Institute of Technology Grant for International Joint Research Supervision / Ph.D. Student: Y. Zhang

• 2015.4-2018.3: Japan Society for the Promotions of Science Grant-in-Aid for Scientific Research on Innovative Areas 15K12003 / High-Quality False-Test-Avoidance Test for Next-Generation Low-Power LSI Circuits

• 2017.1-2017.3: Japan Society for the Promotions Invitation Fellowships for Reserach in Japan / Low-Power-Test-Aware SoC Design for Multi-Core Embedded System (JSPS Fellow: Prof. A. Chakrabarti (University of Calcutta (India))

• 2015.4-2018.3: Japan Society for the Promotions Bilateral Joint Research Projects / High-Quality of LSI Test Methodology based on Checking and Removing Test Clock Risks (Counterpart: University of Stutgart (Germany))

• 2013.4-2017.3: Japan Society for the Promotions of Science Grant-in-Aid for Scientific Research (B) 25280016 / Ultra-Low-Power Built-In Self-Test for LSIs in Implantable Medical Devices

• 2012.4-2015.3: Japan Society for the Promotions of Science Grant-in-Aid for Scientific Research on Innovative Areas 24650022 / Balanced-Switching-Activity Testing

• 2011.3-2015.3: Japan Science and Technology Agency (JST) Japanese-Taiwanese Cooperative Programme on "Nano Device" / Advanced Test Technology Development for Realizing Nano-CMOS LSI Circuits

• 2010.7-2010.8: Japan Society for the Promotions Invitation Fellowships for Reserach in Japan / Low-Power Testing and Testable Design of Advanced Low-Power Semiconductor Devices (JSPS Fellow: Prof. S. Kundu (University of Massachusetts -Amherst (USA))

• 2010.4-2013.3: Japan Society for the Promotions of Science Grant-in-Aid for Scientific Research (B) 22300017 / Power-Adjustment-Based Testing for Next-Generation Low-Power LSI Circuits

• 2007.4-2012.3: Japan Ministry of Education, Culture, Sports and Technolgy: Fukuoka Cluster for Advanced system LSI Technology Development / Yield Improvement Platform for LSI Circuits

• 2009.9-2010.3: Fukuoka Institute of Science and Technology Grant for R&D on Cell-Based Computation / Evaluation Experiment of Using Cell/B.E. for Ultra-Fast Simulation

• 2007.9-2008.3: Japan Ministry of Economy, Trade and Industry Grant for Regional Consortium / Advanced Test Technology for High-Reliability LSI Circuits

• 2007.6-2008.3: STARC Grant for Joint Research / Power-and Noise-Aware Testing

• 2007.4-2010.3: Japan Society for the Promotions of Science Grant-in-Aid for Scientific Research (C) 19500047 / Test Technology for Avoiding Signal Degradation in Next-Generation LSI Circuits

• 2006.4-2007.3: Kyushu Industrial Technology Center Grant for Next-Generation Technology Development / Low-Power Testing for LSI Circuits

• 2005.4-2007.3: Japan Society for the Promotions of Science Grant-in-Aid for Scientific Research (C) 17500039 / Research on Avoiding False Testing for Improving LSI Yields

• 2005.4-2007.3: Japan Science and Technology Agency Fukuoka Plaza Grant for Research Enhancement / Next-Generation LSI Test Design Automation System

• 2006.4-2008.3: Japan Society for the Promotions of Science Grant for Bilateral Joint Research Projects / Highly Reliable LSI Design Methodology Based on Self-Test and Self-Diagnosis

• 2004.4-2005.3: Iizuka City Grant-in-Aid for Scientific Exploration / Fault Diagnosis for LSI Circuits