Frequently Requested Materials
  1. X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita, "On Low-Capture-Power Test Generation for Scan Testing", Proc. of IEEE VLSI Test Symp., pp. 265-270, Palm Springs, USA, May 2005. [PDF] This is the first paper on capture power reduction in at-speed scan testing.
  2. X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Kajihara, P. Girard, and M. Tehranipoor, "Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing", Proc. of IEEE VLSI Test Symp., pp. 166-171, Dana Point, USA, May 2011. [PDF] This is the first paper on capture power safety in at-speed scan testing.
  3. X. Wen, "Power-Aware Testing: The Next Stage", IEEE European Test Symp., Annecy, France, May 29, 2012. [PDF] This is an invited talk providing a comprehensive review of power-aware scan testing of low-power VLSI circuits. A resvised version is available here [PDF].
  4. X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, and L.-T. Wang, "On Pinpoint Capture Power Management in At-Speed Scan Test Generation", Proc. of IEEE Int'l Test Conf., Paper 6.1, Anaheim, USA, Nov. 2012. [PDF] This is the first paper on right power testing in at-speed scan testing to achieve both capture power safety and high test quality.
  5. K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, and and J. Qian, "Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch", Proc. of IEEE Asian Test Symp., pp. 103-108, Bombay, India, Nov. 2015. [PDF] This is the first paper on mitigating the test clock stretch problem in at-speed scan test generation without any hardware overhead.